Messages in this thread |  | | Date | Fri, 10 Jan 1997 11:29:50 -0500 (EST) | From | Jon Lewis <> | Subject | RE: z-Re: Memory deallocation problems |
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On Fri, 10 Jan 1997, Ray Van Tassle-CRV004 wrote:
> Um, nope, you're wrong. The VX chipset will NOT cache more than 64MB. > > Okay, here is the REAL chipset poop, once and for all! > Intel 430HX Intel 430VX VIA Apollo VP-1/VP-2 > Max. Cache 512KB 512KB 2048KB > DRAM Cacheablity 64 or 512MB 64MB 64 or 512MB > EDO Read Timings 4222/5222 5222/6222 4222/5222 > (60/66 mhz) > CPU Write buffer 8QW w/merge 4QW 16QW w/merge > SDRAM support no yes yes
So there's more than one version of "Triton II"? How typical of Intel to create unneeded confusion.
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