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SubjectRe: interrupt counts
Date
Stephen C. Tweedie <sct@dcs.ed.ac.uk> wrote:
: > If you look deep down, at 32-bit machines it will take
: > twice as much work as native size counter handling does.
: > At Alphas I would use 64-bit longs anyway :-)

AFAIK the alpha counters are 32bit, too?

: It's not nearly that bad. The biggest bottleneck is probably memory
: speed, not CPU cycles, and we do all memory transfers in units of
: cache lines already, not words. We'll still just be doing a
: read-modify-write of a single cache line whether the update is for a
: single 32-bit word or a 64-bit doubleword. This is assuming you have
: got a write-back cache, of course; a 486 with write-through cache will
: be a full memory write worse off for the 64-bit counter update.

If we use 32bit counters and test for overflows to increment a second 32 bit
counter we will avoid writing the second 4bytes most of the time.

Greetings
Bernd
--
(OO) -- Bernd_Eckenfels@Wittumstrasse13.76646Bruchsal.de --
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