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SubjectRe: Cache Control
  The patch supplied by Howard C. Tyler to not alter the BIOS setting's of
the CD and NW bits in cr0 is also useful for the Cryrix 486's.

On these CPU's the L1 cache is placed into write back mode (by the BIOS)
when CD=0 & NW=1 (an illegal combination on intel CPU's). As linux
currently stands, it always forces the cache into write through mode.

This saves be sending in essentially the same patch, since I've been
playing with a lot of the Cyrix chips in the last week (and have a databook).

It's also possible to detect the version of the Cyrix chip (DX or DX2) and
mask revision via I/O instructions. Linus, would a patch to detect and
report this via /proc/cpuinfo be accepted?

I imagine that the display of cr0 would be just as useful if it came from
/proc/cpuinfo (as opposed to RALT-Scroll-Lock) since I don't _think_ it's
modified after startup.

Derek Fawcus (G7FVS)

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