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SubjectRe: Triton chipset & bridge optimizing
On 18 Mar 96 at 23:38, Gerard Roudier wrote:

>
> Graham,
>
> I have an Intel plato board (Neptune Chipset).
> In order to show and to tune the chipset I have build a command tool.
> As the ncrBsd2Linux driver, it was first for my own usage.
> It seems that you have the same problem.
>
> Here is the source code.
> It's mix of "scanpci.c" by Robin Cutshaw and FreeBSD "pcisupport.c" by
> Stefan Esser. (I only use excellent source code).
> Compile the following source under Linux and run it.

<snip a lot of scarey source code...:))>

The output from the program is as follows.....

CPU: Pentium, 60MHz, CPU->Memory posting ON, read around write
Warning: Cache parity disabled!
Cache: 256KB writeback, cache clocks=3-2-2-2/4-2-2-2
Cache flags: cache-all byte-control
DRAM: memory clocks=X-4-4-4 (70ns)
CPU->PCI: posting ON, burst mode ON, PCI clocks=2-1-1-1
PCI->Memory: posting ON
Refresh: RAS#Only BurstOf4

Looks like the writeback cache is on from this, however this seems at
variance with dmesg info about L2 cache not being supported. Does
23.96 bogomips seem the right ballpark for a 60MHz Pentium.....?


Graham

Ask not what you can do for your country,
but what your government is doing to you


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