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SubjectRe: IPv6 and the "average user"

On Wed, 27 Nov 1996, Phillip Dillinger wrote:
> Processing power should not be a problem. A ten port 100Mbps router, with an
> aggregate bandwidth of 1Gbps, needs to route only about 651041 packets/second.
> Specialized hardware and a fast backplane could handle this very easily. The
> problem with processing power and routers as they are now is that they not
> only process the header, but also the payload. This is unneccesary for a
> router to do, and a good way to handle that is to have separate backplanes
> for the headers and the payloads, and to only process the headers.


Nice idea. Although you still have to re-integrate the
Headers with their respective payloads. And at the speeds
the Backbone -will- be using it is not an easy endevore.
NOT impossible, Just not easy.

Would someone like to layout a dual PCI bus system
along the line of the above ?

I'd really like to see what some of you might come up with to
re-integrate the headers/payloads, IE: both hardware & soft.


PS: I have a few ideas although nothing specific yet.
| James W. Laferriere | Network Engineer |
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| 25416 - 22nd S. | Kent, WA 98032 |
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Instead of a dual PCI bus system, it would be better to have headers go over
PCI, and then have payloads get stored on a content-addresable memory or
similar until their headers are ready. Then they can be bonded, like this:

------------ ---------------------------------
| | Payloads | Integrator (CAM+logic) |
| NIC |-------------------------------| Puts together payloads |
| | | with their respective headers |
------------ ---------------------------------
| | |
| PCI bus (headers) | |
-------------------------------------------------- -------------
| | DeMux |
| -------------
------------------- --------------- | | | | |
| | | | Outputs
| Processing Unit |----------| Memory |
| (Routes) | ---------------

This simplification shows the basic principle. Much of this is hardware.
It works thusly:

1. Packet is recieved and then tore apart into payloads and headers. They
are both stamped with a unique time-code.
2. Then, the payload gets stored, and the header gets processed. As a
special case, if the header says that the payload has routing info, the
processing unit gets the payload using the unique timecode and then
processes it.
3. If the header is processed, it gets sent to the Integrator. The
integrator then combines the header and the payload having the same
time-code to make a fully-formed packet.
4. Then the multiplexed aggregate data stream is demuxed to each
individual output port. This completes the routing.

There are some ways to improve this, too. Multiple processing units can be
used using the same global routing table, and very close to n-fold
performance can be reached. ( It would not be n-fold because of variations
in header processing times ) Also, the serial nature of the incoming and
outgoing datastream to the processing unit allows serial IO. This means that
bandwidth is not limited by the PCI bus. With special processor-IO glue
logic, it would be possible to use any other backplane, or possibly a serial

Phillip Dillinger

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