Messages in this thread |  | | Date | Tue, 17 Dec 1996 11:44:19 +0000 (GMT/BST) | From | Mike Jagdis <> | Subject | Re: Cyrix 6x86 - wierd problem |
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> The previous settings, which failed, were:- > CONFIG_CYRIX=y > CONFIG_CYRIX_5X86=y > CONFIG_CYRIX_6X86=y > # CONFIG_CYRIX_6X86_VSPM is not set > CONFIG_CYRIX_6X86_L1_BROKEN=y > > I do not know whether its the L1 cache setting or the 6X86 features (the > 5X86 features *should* have no effect). There is obviously something > slightly screwy here....
Ah, disabling the L1 cache would explain the slow down (this option should disappear in future - the "L1 cache problem" appears to have been overrated). It would also stress your L2 cache somewhat more too - which could exercise motherboard problems due to poor signal quality (the L1 cache problem was, allegedly, down to a non-Cyrix approved, poor quality motherboard - maybe...).
The other likely looking possibility is allowing the branch table to cache far branches (which I've only seen documented by IBM, not Cyrix - although it appears to work fine on a 1 rev6 chip). You can comment out the code that enables this in arch/i386/head.S by putting an "#if 0" just before the bit that enables the debug registers and an"#endif" just before the "sti" further down.
Mike
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