[lkml]   [1996]   [Dec]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: Cyrix 6x86 - wierd problem

> The previous settings, which failed, were:-
> # CONFIG_CYRIX_6X86_VSPM is not set
> I do not know whether its the L1 cache setting or the 6X86 features (the
> 5X86 features *should* have no effect). There is obviously something
> slightly screwy here....

Ah, disabling the L1 cache would explain the slow down (this option
should disappear in future - the "L1 cache problem" appears to have
been overrated). It would also stress your L2 cache somewhat more
too - which could exercise motherboard problems due to poor signal
quality (the L1 cache problem was, allegedly, down to a non-Cyrix
approved, poor quality motherboard - maybe...).

The other likely looking possibility is allowing the branch table
to cache far branches (which I've only seen documented by IBM, not
Cyrix - although it appears to work fine on a 1 rev6 chip). You can
comment out the code that enables this in arch/i386/head.S by putting
an "#if 0" just before the bit that enables the debug registers and
an"#endif" just before the "sti" further down.


| Mike Jagdis | Internet: |
| Roan Technology Ltd. | |
| 54A Peach Street, Wokingham | Telephone: +44 118 989 0403 |
| RG40 1XG, ENGLAND | Fax: +44 118 989 1195 |

 \ /
  Last update: 2005-03-22 13:37    [W:0.045 / U:1.156 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site