Messages in this thread |  | | Date | Sat, 23 Nov 1996 14:08:15 +0000 (GMT) | From | Mark Hemment <> | Subject | Re: IP Checksumming |
| |
On Fri, 22 Nov 1996, Richard B. Johnson wrote: > > On Sat, 23 Nov 1996, Alan Cox wrote: > > > > > My numbers agree with Tom May's give or take 5%. > > > > Alan > > > That's what I really enjoy about persons who know everything. They usually > show great intellectual capacity. Use the Pentium's internal cycle-counter > to test something before you state "His code craps all over yours...". >
The problem with people who know everything is that they are usually right.
My 'good turn' for the day has been to knock up a little test harness, using the cycle counters and with interrupts off (happy?), to test your checksum code against the original. I've included the numbers below. They speak for themselves - provided I haven't made a big mistake - you lose big time Richard.
For each 'size', the harness tests the memory starting at a variety of different offsets and uses the "wbinvd" to flush the L1 cache (which may, or may not, flush your L2 cache). I've even made a patch available from http://www.nextd.demon.co.uk if you want to check the code (its not perfect, just a quick hack). Simply install, and "cat /proc/tcp_test" to perform the tests and get the results.
Regards, markhe
"Orig" is the Original checksum code. "lodsw" is Richards suggested improvment. For each result, the first number is the best found, the second the worst (tested over several different starting offsets).
IP Checksum: Cycles for mem size 100; Cache Primed For Orig: 72/197 For lodsw: 433/500 Cycles for mem size 512; Cache Primed For Orig: 195/240 For lodsw: 2081/2085 Cycles for mem size 924; Cache Primed For Orig: 342/359 For lodsw: 3729/3733 Cycles for mem size 1336; Cache Primed For Orig: 469/486 For lodsw: 5377/5381 Cycles for mem size 1748; Cache Primed For Orig: 596/610 For lodsw: 7025/7025 Cycles for mem size 2160; Cache Primed For Orig: 723/737 For lodsw: 8673/8673 Cycles for mem size 2572; Cache Primed For Orig: 850/889 For lodsw: 10321/10324 Cycles for mem size 2984; Cache Primed For Orig: 977/994 For lodsw: 11969/11972 Cycles for mem size 3396; Cache Primed For Orig: 1096/1135 For lodsw: 13617/13621 Cycles for mem size 3808; Cache Primed For Orig: 1221/1270 For lodsw: 15265/15269 Cycles for mem size 4220; Cache Primed For Orig: 1372/1421 For lodsw: 16913/16930 Cycles for mem size 4632; Cache Primed For Orig: 1499/1572 For lodsw: 18561/18594 Cycles for mem size 5044; Cache Primed For Orig: 1658/1705 For lodsw: 20225/20246 Cycles for mem size 5456; Cache Primed For Orig: 1785/1864 For lodsw: 21873/21906 Cycles for mem size 5868; Cache Primed For Orig: 1936/1991 For lodsw: 23537/23554 Cycles for mem size 6280; Cache Primed For Orig: 2103/2166 For lodsw: 25201/25234 Cycles for mem size 6692; Cache Primed For Orig: 2229/2295 For lodsw: 26849/26882 Cycles for mem size 100; Cache Flushed For Orig: 203/238 For lodsw: 505/509 Cycles for mem size 512; Cache Flushed For Orig: 508/605 For lodsw: 2249/2257 Cycles for mem size 924; Cache Flushed For Orig: 834/940 For lodsw: 4001/4009 Cycles for mem size 1336; Cache Flushed For Orig: 1143/1269 For lodsw: 5753/5761 Cycles for mem size 1748; Cache Flushed For Orig: 1452/1604 For lodsw: 7505/7512 Cycles for mem size 2160; Cache Flushed For Orig: 1761/1931 For lodsw: 9257/9257 Cycles for mem size 2572; Cache Flushed For Orig: 2061/2254 For lodsw: 11009/11009 Cycles for mem size 2984; Cache Flushed For Orig: 2371/2581 For lodsw: 12761/12881 Cycles for mem size 3396; Cache Flushed For Orig: 2679/3063 For lodsw: 14513/14513 Cycles for mem size 3808; Cache Flushed For Orig: 2980/3283 For lodsw: 16257/16265 Cycles for mem size 4220; Cache Flushed For Orig: 3306/3618 For lodsw: 18009/18017 Cycles for mem size 4632; Cache Flushed For Orig: 3615/4087 For lodsw: 19761/19769 Cycles for mem size 5044; Cache Flushed For Orig: 3924/4282 For lodsw: 21513/21520 Cycles for mem size 5456; Cache Flushed For Orig: 4233/4609 For lodsw: 23265/23265 Cycles for mem size 5868; Cache Flushed For Orig: 4533/5078 For lodsw: 25017/25017 Cycles for mem size 6280; Cache Flushed For Orig: 4843/5259 For lodsw: 26769/26769 Cycles for mem size 6692; Cache Flushed For Orig: 5151/5594 For lodsw: 28521/28671
|  |