Messages in this thread Patch in this message |  | | Subject | [patch / 2.1.10] Rip roaring vga | Date | Sat, 16 Nov 1996 20:35:42 -0500 (EST) | From | "Aaron Tiensivu" <> |
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I don't think this really should go into the standard kernel, but it "seems" to make a bit of a difference on my ATI Mach32 video card.. it incorperates the scrolling patch from the list earlier (I forgot who, sorry!) and removes the pauses when doing io to/from the card.
Any 'decent' new video card should handle it fine. An option in vga.c that is largely ignored, that works on most video cards, is the "VGA_CAN_DO_64KB".. allows a larger scrollback buffer.. definite plus.
Either way, here's the patch:
--- linux/drivers/char/vga.c.virgin Sat Nov 16 20:19:17 1996 +++ linux/drivers/char/vga.c Sat Nov 16 20:27:10 1996 @@ -79,10 +79,10 @@ return ;
for (i=j=0; i<16; i++) { - outb_p (color_table[i], dac_reg) ; - outb_p (vc_cons[fg_console].d->vc_palette[j++]>>2, dac_val) ; - outb_p (vc_cons[fg_console].d->vc_palette[j++]>>2, dac_val) ; - outb_p (vc_cons[fg_console].d->vc_palette[j++]>>2, dac_val) ; + outb (color_table[i], dac_reg) ; + outb (vc_cons[fg_console].d->vc_palette[j++]>>2, dac_val) ; + outb (vc_cons[fg_console].d->vc_palette[j++]>>2, dac_val) ; + outb (vc_cons[fg_console].d->vc_palette[j++]>>2, dac_val) ; } }
@@ -90,15 +90,17 @@ __set_origin(unsigned short offset) { unsigned long flags; + unsigned short high, low;
clear_selection();
+ high = 12 + (offset & 0xff00); + low = 13 + (offset << 8); + save_flags(flags); cli(); __origin = offset; - outb_p(12, video_port_reg); - outb_p(offset >> 8, video_port_val); - outb_p(13, video_port_reg); - outb_p(offset, video_port_val); + outw(high, video_port_reg); + outw(low, video_port_reg); restore_flags(flags); }
@@ -111,10 +113,10 @@ /* This is inefficient, we could just put the cursor at 0xffff, but perhaps the delays due to the inefficiency are useful for some hardware... */ - outb_p(14, video_port_reg); - outb_p(0xff&((video_mem_term-video_mem_base)>>9), video_port_val); - outb_p(15, video_port_reg); - outb_p(0xff&((video_mem_term-video_mem_base)>>1), video_port_val); + outb(14, video_port_reg); + outb(0xff&((video_mem_term-video_mem_base)>>9), video_port_val); + outb(15, video_port_reg); + outb(0xff&((video_mem_term-video_mem_base)>>1), video_port_val); }
void @@ -128,10 +130,10 @@ __set_origin(__real_origin); save_flags(flags); cli(); if (deccm) { - outb_p(14, video_port_reg); - outb_p(0xff&((pos-video_mem_base)>>9), video_port_val); - outb_p(15, video_port_reg); - outb_p(0xff&((pos-video_mem_base)>>1), video_port_val); + outb(14, video_port_reg); + outb(0xff&((pos-video_mem_base)>>9), video_port_val); + outb(15, video_port_reg); + outb(0xff&((pos-video_mem_base)>>1), video_port_val); } else hide_cursor(); restore_flags(flags); @@ -191,8 +193,8 @@ */ video_mem_base = 0xa0000 ; video_mem_term = 0xb0000 ; - outb_p (6, 0x3ce) ; - outb_p (6, 0x3cf) ; + outb (6, 0x3ce) ; + outb (6, 0x3cf) ; #endif
/* @@ -202,20 +204,20 @@ */
for (i=0; i<16; i++) { - inb_p (0x3da) ; - outb_p (i, 0x3c0) ; - outb_p (i, 0x3c0) ; + inb (0x3da) ; + outb (i, 0x3c0) ; + outb (i, 0x3c0) ; } - outb_p (0x20, 0x3c0) ; + outb (0x20, 0x3c0) ;
/* now set the DAC registers back to their * default values */
for (i=0; i<16; i++) { - outb_p (color_table[i], 0x3c8) ; - outb_p (default_red[i], 0x3c9) ; - outb_p (default_grn[i], 0x3c9) ; - outb_p (default_blu[i], 0x3c9) ; + outb (color_table[i], 0x3c8) ; + outb (default_red[i], 0x3c9) ; + outb (default_grn[i], 0x3c9) ; + outb (default_blu[i], 0x3c9) ; } } } @@ -372,21 +374,21 @@ #endif
cli(); - outb_p( 0x00, seq_port_reg ); /* First, the sequencer */ - outb_p( 0x01, seq_port_val ); /* Synchronous reset */ - outb_p( 0x02, seq_port_reg ); - outb_p( 0x04, seq_port_val ); /* CPU writes only to map 2 */ - outb_p( 0x04, seq_port_reg ); - outb_p( 0x07, seq_port_val ); /* Sequential addressing */ - outb_p( 0x00, seq_port_reg ); - outb_p( 0x03, seq_port_val ); /* Clear synchronous reset */ - - outb_p( 0x04, gr_port_reg ); /* Now, the graphics controller */ - outb_p( 0x02, gr_port_val ); /* select map 2 */ - outb_p( 0x05, gr_port_reg ); - outb_p( 0x00, gr_port_val ); /* disable odd-even addressing */ - outb_p( 0x06, gr_port_reg ); - outb_p( 0x00, gr_port_val ); /* map start at A000:0000 */ + outb( 0x00, seq_port_reg ); /* First, the sequencer */ + outb( 0x01, seq_port_val ); /* Synchronous reset */ + outb( 0x02, seq_port_reg ); + outb( 0x04, seq_port_val ); /* CPU writes only to map 2 */ + outb( 0x04, seq_port_reg ); + outb( 0x07, seq_port_val ); /* Sequential addressing */ + outb( 0x00, seq_port_reg ); + outb( 0x03, seq_port_val ); /* Clear synchronous reset */ + + outb( 0x04, gr_port_reg ); /* Now, the graphics controller */ + outb( 0x02, gr_port_val ); /* select map 2 */ + outb( 0x05, gr_port_reg ); + outb( 0x00, gr_port_val ); /* disable odd-even addressing */ + outb( 0x06, gr_port_reg ); + outb( 0x00, gr_port_val ); /* map start at A000:0000 */ sti();
if (arg) @@ -424,26 +426,26 @@ }
cli(); - outb_p( 0x00, seq_port_reg ); /* First, the sequencer */ - outb_p( 0x01, seq_port_val ); /* Synchronous reset */ - outb_p( 0x02, seq_port_reg ); - outb_p( 0x03, seq_port_val ); /* CPU writes to maps 0 and 1 */ - outb_p( 0x04, seq_port_reg ); - outb_p( 0x03, seq_port_val ); /* odd-even addressing */ + outb( 0x00, seq_port_reg ); /* First, the sequencer */ + outb( 0x01, seq_port_val ); /* Synchronous reset */ + outb( 0x02, seq_port_reg ); + outb( 0x03, seq_port_val ); /* CPU writes to maps 0 and 1 */ + outb( 0x04, seq_port_reg ); + outb( 0x03, seq_port_val ); /* odd-even addressing */ if (set) { - outb_p( 0x03, seq_port_reg ); /* Character Map Select */ - outb_p( font_select, seq_port_val ); + outb( 0x03, seq_port_reg ); /* Character Map Select */ + outb( font_select, seq_port_val ); } - outb_p( 0x00, seq_port_reg ); - outb_p( 0x03, seq_port_val ); /* clear synchronous reset */ + outb( 0x00, seq_port_reg ); + outb( 0x03, seq_port_val ); /* clear synchronous reset */
- outb_p( 0x04, gr_port_reg ); /* Now, the graphics controller */ - outb_p( 0x00, gr_port_val ); /* select map 0 for CPU */ - outb_p( 0x05, gr_port_reg ); - outb_p( 0x10, gr_port_val ); /* enable even-odd addressing */ - outb_p( 0x06, gr_port_reg ); - outb_p( beg, gr_port_val ); /* map starts at b800:0 or b000:0 */ + outb( 0x04, gr_port_reg ); /* Now, the graphics controller */ + outb( 0x00, gr_port_val ); /* select map 0 for CPU */ + outb( 0x05, gr_port_reg ); + outb( 0x10, gr_port_val ); /* enable even-odd addressing */ + outb( 0x06, gr_port_reg ); + outb( beg, gr_port_val ); /* map starts at b800:0 or b000:0 */
/* if 512 char mode is already enabled don't re-enable it. */ if ((set)&&(ch512!=ch512enabled)) /* attribute controller */ @@ -451,13 +453,13 @@ ch512enabled=ch512; /* 256-char: enable intensity bit 512-char: disable intensity bit */ - inb_p( video_port_status ); /* clear address flip-flop */ - outb_p ( 0x12, attrib_port ); /* color plane enable register */ - outb_p ( ch512 ? 0x07 : 0x0f, attrib_port ); + inb( video_port_status ); /* clear address flip-flop */ + outb ( 0x12, attrib_port ); /* color plane enable register */ + outb ( ch512 ? 0x07 : 0x0f, attrib_port ); /* Wilton (1987) mentions the following; I don't know what it means, but it works, and it appears necessary */ - inb_p( video_port_status ); - outb_p ( 0x20, attrib_port ); + inb( video_port_status ); + outb ( 0x20, attrib_port ); } sti();
@@ -502,14 +504,14 @@ are all don't care bits on EGA, so I guess it doesn't matter. */
cli(); - outb_p( 0x07, video_port_reg ); /* CRTC overflow register */ - ovr = inb_p(video_port_val); - outb_p( 0x09, video_port_reg ); /* Font size register */ - fsr = inb_p(video_port_val); - outb_p( 0x0a, video_port_reg ); /* Cursor start */ - curs = inb_p(video_port_val); - outb_p( 0x0b, video_port_reg ); /* Cursor end */ - cure = inb_p(video_port_val); + outb( 0x07, video_port_reg ); /* CRTC overflow register */ + ovr = inb(video_port_val); + outb( 0x09, video_port_reg ); /* Font size register */ + fsr = inb(video_port_val); + outb( 0x0a, video_port_reg ); /* Cursor start */ + curs = inb(video_port_val); + outb( 0x0b, video_port_reg ); /* Cursor end */ + cure = inb(video_port_val); sti();
vde = maxscan & 0xff; /* Vertical display end reg */ @@ -521,16 +523,16 @@ cure = (cure & 0xe0) + fontheight - (fontheight < 10 ? 1 : 2);
cli(); - outb_p( 0x07, video_port_reg ); /* CRTC overflow register */ - outb_p( ovr, video_port_val ); - outb_p( 0x09, video_port_reg ); /* Font size */ - outb_p( fsr, video_port_val ); - outb_p( 0x0a, video_port_reg ); /* Cursor start */ - outb_p( curs, video_port_val ); - outb_p( 0x0b, video_port_reg ); /* Cursor end */ - outb_p( cure, video_port_val ); - outb_p( 0x12, video_port_reg ); /* Vertical display limit */ - outb_p( vde, video_port_val ); + outb( 0x07, video_port_reg ); /* CRTC overflow register */ + outb( ovr, video_port_val ); + outb( 0x09, video_port_reg ); /* Font size */ + outb( fsr, video_port_val ); + outb( 0x0a, video_port_reg ); /* Cursor start */ + outb( curs, video_port_val ); + outb( 0x0b, video_port_reg ); /* Cursor end */ + outb( cure, video_port_val ); + outb( 0x12, video_port_reg ); /* Vertical display limit */ + outb( vde, video_port_val ); sti();
if ( rows == video_num_lines ) { --- Which is worse: ignorance or apathy? Who knows? Who cares?
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