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From
SubjectRe: Extending task_struct with a task_queue ?
Date
Hi

>> The following problem is similar to switching the FPU context:
>> I'm using a framegrabber, which provides 8 Lookup-Tables.
>> Every Task which uses the grabber can have a private LUT.
>> So its necessary to switch the LUT on Task Switches if the
>> next task uses a different LUT.
>> What about adding a task_queue to the task-struct which
>> is executed before switch_to(task_xy); ?
>> Any comments, or suggestions how to do this without
>> changes in Kernel ?
>
> Putting a task queue in there is possibly not good. Thats very performance
> critical code. Do devices do read/write etc calls to the frame grabber and
> if so can you delay the switch akin to delaying FPU state.

As long as everything is done in Kernel space there is no problem, because
I can delay the task switches as long as I want. But it is very ugly
to do everything in kernel-space.
But when I want to access the Framebuffer from User-Space, I have a problem.
Semaphores are not good, because I need the system for doing Data-Aquisition
in realtime.

> If it is mmaped
> you may be able to do the same by unmapping and remapping pages for the
> 8 maps.

Here how it works: The Databus of the framebuffer is connected with
the Addressbus of a SRAM. The Databus of the SRAM is connected to
the PCI-(Data)Bus, so a tranlation of colortab can be done.
I need two or three different colortabs at the same time.
Switching colortab is done by writing a number to the LUT-Control-
Register, which is connected to A8...A10 of the SRAM.
If I want a private Colortab for every task, I have to
write the number of the colortab to Lut-Select before Task-
switches.



------------------------
I I
I I
I Framebuffer I
I I
I I
------------------------
| D0...D7
|
|
| A0..A7
------------------------ -----------------
I I A8..A10 I I
I SRAM I------------I Lut-Select I
I I I I
------------------------ -----------------
| D0..D7
|
|
----------------------
PCI-BUS
----------------------

In reality there are four LUT-Lanes (four SRAMS),
because the Bus is 32 Bit, and four Bytes have to be translated.


Jochen


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http://wpfd25.physik.uni-wuerzburg.de/~karrer/xgras/xgras.html

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