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Messages in this thread Complete thread (EXPERIMENTAL) |
On Thu, 2002-12-12 at 10:42, Terje Eggestad wrote:
It takes about 11 cycles on athlon, 34 on PII, and a whooping 84 on P4.
For a simple op like that, even 11 is a lot... Really makes you wonder. wasn't rdtsc also supposed to be a pipeline sync of the cpu? (or am I confusing it with cpuid) THis is what the P4 manual says: "The RDTSC instruction is not a serializing instruction. Thus, it does not necessarily wait until all previous instructions have been executed before reading the counter. Similarly, subsequent instructions may begin execution before the read operation is performed." Thus it *shouldn't* sync the pipeline. cpuid is a serializing inst, yes. TJ -- _________________________________________________________________________ Terje Eggestad mailto:terje.eggestad@scali.no Scali Scalable Linux Systems http://www.scali.com Olaf Helsets Vei 6 tel: +47 22 62 89 61 (OFFICE) P.O.Box 150, Oppsal +47 975 31 574 (MOBILE) N-0619 Oslo fax: +47 22 62 89 51 NORWAY _________________________________________________________________________ | ||||||||||
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