Messages in this thread | | | Date | Tue, 7 May 2024 12:25:07 -0400 | Subject | Re: [PATCH v2 09/16] x86/mce: Unify AMD THR handler with MCA Polling | From | Yazen Ghannam <> |
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On 5/4/24 10:52 AM, Borislav Petkov wrote: > On Mon, Apr 29, 2024 at 10:36:57AM -0400, Yazen Ghannam wrote: >> Related to this, I've been thinking that banks with thresholding enabled >> should be removed from the list of polling banks. This is done on Intel but >> not on AMD. >> >> I wanted to give it more thought, because I think folks have come to expect >> polling and thresholding to be independent on AMD. > > Yes, this whole thing sounds weird. > > On the one hand, you have a special interrupt for errors which have > reached a threshold *just* *so* you don't have to poll. Because polling > is ok but getting a a special interrupt is better and such notification > systems always want to have a special interrupt and not have to poll. > > On the other hand, you're marrying the two which sounds weird. Why? > > What is wrong with getting thresholding interrupts? >
Nothing. This patch is not disabling the interrupt. The goal is to get rid of duplicate code and have a single function that checks the MCA banks.
This would be similar to intel_threshold_interrupt().
> Why can't we simply stop the polling and do THR only if available? That > would save a lot of energy. > > So why can't we program the THR to raise an interrupt on a single error > and disable polling completely? > > Because that would be a lot better as the hardware would be doing the > work for us. > > In any case, I'm missing the strategy here so no cleanups without > a clear goal first please. >
We could do that. In fact, there's a request to use the threshold that is pre-programmed in the hardware. And we could use some of the current kernel parameters for overrides, if needed.
Thanks, Yazen
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