lkml.org 
[lkml]   [2024]   [Apr]   [9]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Date
    Subject[PATCH v3 18/18] arm64: dts: mediatek: add audio support for mt8365-evk
    Add the sound node which is linked to the MT8365 SoC AFE and
    the MT6357 audio codec.

    Update the file header.

    Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
    ---
    arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 98 +++++++++++++++++++++++++++--
    1 file changed, 94 insertions(+), 4 deletions(-)

    diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
    index 50cbaefa1a99..eb0c5f076dd4 100644
    --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
    +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
    @@ -1,9 +1,9 @@
    // SPDX-License-Identifier: GPL-2.0
    /*
    - * Copyright (c) 2021-2022 BayLibre, SAS.
    - * Authors:
    - * Fabien Parent <fparent@baylibre.com>
    - * Bernhard Rosenkränzer <bero@baylibre.com>
    + * Copyright (c) 2024 BayLibre, SAS.
    + * Authors: Fabien Parent <fparent@baylibre.com>
    + * Bernhard Rosenkränzer <bero@baylibre.com>
    + * Alexandre Mergnat <amergnat@baylibre.com>
    */

    /dts-v1/;
    @@ -86,6 +86,29 @@ optee_reserved: optee@43200000 {
    reg = <0 0x43200000 0 0x00c00000>;
    };
    };
    +
    + sound: sound {
    + compatible = "mediatek,mt8365-mt6357";
    + pinctrl-names = "default",
    + "dmic",
    + "miso_off",
    + "miso_on",
    + "mosi_off",
    + "mosi_on";
    + pinctrl-0 = <&aud_default_pins>;
    + pinctrl-1 = <&aud_dmic_pins>;
    + pinctrl-2 = <&aud_miso_off_pins>;
    + pinctrl-3 = <&aud_miso_on_pins>;
    + pinctrl-4 = <&aud_mosi_off_pins>;
    + pinctrl-5 = <&aud_mosi_on_pins>;
    + mediatek,platform = <&afe>;
    + status = "okay";
    + };
    +};
    +
    +&afe {
    + mediatek,dmic-mode = <1>;
    + status = "okay";
    };

    &cpu0 {
    @@ -174,6 +197,12 @@ &mmc1 {
    status = "okay";
    };

    +&mt6357_codec {
    + mediatek,micbias0-microvolt = <1900000>;
    + mediatek,micbias1-microvolt = <1700000>;
    + mediatek,vaud28-supply = <&mt6357_vaud28_reg>;
    +};
    +
    &mt6357_pmic {
    interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-controller;
    @@ -181,6 +210,67 @@ &mt6357_pmic {
    };

    &pio {
    + aud_default_pins: audiodefault-pins {
    + pins {
    + pinmux = <MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK>,
    + <MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK>,
    + <MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK>,
    + <MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO>;
    + };
    + };
    +
    + aud_dmic_pins: audiodmic-pins {
    + pins {
    + pinmux = <MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK>,
    + <MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0>,
    + <MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1>;
    + };
    + };
    +
    + aud_miso_off_pins: misooff-pins {
    + pins {
    + pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53>,
    + <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54>,
    + <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55>,
    + <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56>;
    + input-enable;
    + bias-pull-down;
    + drive-strength = <MTK_DRIVE_2mA>;
    + };
    + };
    +
    + aud_miso_on_pins: misoon-pins {
    + pins {
    + pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO>,
    + <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO>,
    + <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0>,
    + <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1>;
    + drive-strength = <MTK_DRIVE_6mA>;
    + };
    + };
    +
    + aud_mosi_off_pins: mosioff-pins {
    + pins {
    + pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49>,
    + <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50>,
    + <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51>,
    + <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52>;
    + input-enable;
    + bias-pull-down;
    + drive-strength = <MTK_DRIVE_2mA>;
    + };
    + };
    +
    + aud_mosi_on_pins: mosion-pins {
    + pins {
    + pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI>,
    + <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI>,
    + <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0>,
    + <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1>;
    + drive-strength = <MTK_DRIVE_6mA>;
    + };
    + };
    +
    ethernet_pins: ethernet-pins {
    phy_reset_pins {
    pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
    --
    2.25.1


    \
     
     \ /
      Last update: 2024-05-27 16:31    [W:2.904 / U:0.004 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site