Messages in this thread | ![/](/images/icornerl.gif) | | Date | Tue, 9 Apr 2024 16:01:15 +0100 | From | Conor Dooley <> | Subject | Re: [PATCH v1 0/6] SiFive cache controller PMU drivers |
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On Fri, Feb 16, 2024 at 10:05:04AM +0000, Conor Dooley wrote: > On Thu, Feb 15, 2024 at 04:08:12PM -0800, Samuel Holland wrote: > > > All three of these cache controllers (with PMUs) have been integrated in > > SoCs by our customers. However, as none of those SoCs have been publicly > > announced yet, I cannot include SoC-specific compatible strings in this > > version of the devicetree bindings. > > And I don't want to apply any of those dt-binding patches until then. > Stuff like "sifive,perfmon-counters" seems like a property that would > go away with a device-specific compatible, at least for the ccache.
Reading the P550 stuff today reminded me that I had not got around to looking at this series again. You should be able to use that to satisfy my wish for some soc-specific compatibles, right?
And w.r.r. the perfmon-counters property, looked to me like Rob was proposing it not even having to be vendor specific. [unhandled content-type:application/pgp-signature] | ![\](/images/icornerr.gif) |