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SubjectRe: [PATCH v9 3/6] dt-bindings: pci: qcom: Add opp table
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Ack to all the comments. I will modify them in next patch series.

- Krishna Chaitanya.

On 4/7/2024 8:12 PM, Manivannan Sadhasivam wrote:
> On Sun, Apr 07, 2024 at 10:07:36AM +0530, Krishna chaitanya chundru wrote:
>
> s/opp/OPP
>
>> PCIe needs to choose the appropriate performance state of RPMH power
>
> s/RPMH/RPMh
>
>> domain based upon the PCIe gen speed.
>>
>
> s/upon/on
>
>> Adding the Operating Performance Points table allows to adjust power
>> domain performance state and icc peak bw, depending on the PCIe gen
>
> s/icc/ICC
>
> s/PCIe gen speed/PCIe data rate
>
>> speed and width.
>>
>
> s/width/link width
>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>
> With above changes,
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> - Mani
>
>> ---
>> Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
>> index 1496d6993ab4..d8c0afaa4b19 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
>> @@ -69,6 +69,10 @@ properties:
>> - const: msi6
>> - const: msi7
>>
>> + operating-points-v2: true
>> + opp-table:
>> + type: object
>> +
>> resets:
>> maxItems: 1
>>
>>
>> --
>> 2.42.0
>>
>

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