Messages in this thread | | | From | Krzysztof Kozlowski <> | Subject | Re: [PATCH v3 0/3] arm64: dts: hi3798cv200: fix GICR size, add cache info, maintenance irq and GICH, GICV spaces | Date | Mon, 8 Apr 2024 09:31:03 +0200 |
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On Mon, 19 Feb 2024 23:05:25 +0800, Yang Xiwen wrote: > The patchset fixes some warnings reported by the kernel during boot. > > The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section > 2.2.1 Master Processor. > > The cache line size and the set-associative info are from Cortex-A53 > Documentation [2]. > > [...]
It's rc3 and almost one month after last ping/talk, so apparently these got lost. I'll take them, but let me know if this should go via different tree.
Applied, thanks!
[1/3] arm64: dts: hi3798cv200: fix the size of GICR https://git.kernel.org/krzk/linux-dt/c/428a575dc9038846ad259466d5ba109858c0a023 [2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq https://git.kernel.org/krzk/linux-dt/c/f00a6b9644a5668e25ad9ca5aff53b6de4b0aaf6 [3/3] arm64: dts: hi3798cv200: add cache info https://git.kernel.org/krzk/linux-dt/c/c7a3ad884d1dc1302dcc3295baa18917180b8bec
Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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