Messages in this thread | | | From | "Zhang, Rui" <> | Subject | Re: [PATCH 1/3] thermal: intel: intel_tcc: Add model checks for temperature registers | Date | Sun, 7 Apr 2024 08:13:28 +0000 |
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> + > +#define TCC_FAM6_MODEL_TEMP_MASKS
Future non FAM6 processors can still use this macro, right? So I'd prefer to remove FAM6_MODEL in the macro name.
[...] > > + > +/** > + * get_tcc_offset_mask() - Returns the model-specific bitmask for > TCC offset > + * > + * Get the model-specific bitmask to extract TCC_OFFSET from the > MSR_TEMPERATURE_ > + * TARGET register. If the mask is 0, it means the processor does > not support TCC offset. > + * > + * Return: The model-specific bitmask for TCC offset. > + */ > +u32 get_tcc_offset_mask(void) > +{ > + return intel_tcc_temp_masks.tcc_offset; > +} > +EXPORT_SYMBOL_NS(get_tcc_offset_mask, INTEL_TCC);
the name is not consistent with the other intel_tcc APIs.
how about intel_tcc_get_offset_mask()?
[...]
> diff --git a/include/linux/intel_tcc.h b/include/linux/intel_tcc.h > index 8ff8eabb4a98..e281cf06aeab 100644 > --- a/include/linux/intel_tcc.h > +++ b/include/linux/intel_tcc.h > @@ -14,5 +14,13 @@ int intel_tcc_get_tjmax(int cpu); > int intel_tcc_get_offset(int cpu); > int intel_tcc_set_offset(int cpu, int offset); > int intel_tcc_get_temp(int cpu, int *temp, bool pkg); > +#ifdef CONFIG_INTEL_TCC > +u32 get_tcc_offset_mask(void); > +u32 intel_tcc_get_temp_mask(bool pkg); > +#else > +static inline u32 get_tcc_offset_mask(void) { return 0; } > +/* Use the architectural bitmask of the temperature readout. No > model checks. */ > +static inline u32 intel_tcc_get_temp_mask(bool pkg) { return 0x7f; } > +#endif
for intel_tcc_get_temp_mask() 1. with CONFIG_INTEL_TCC a) for a platform in the model list, return the hardcoded value b) for a platform not in the model list, return 0xff 2. without CONFIG_INTEL_TCC, return 0x7f
This is a bit confusing. IMO, at least we should leave a comment about this difference.
thanks, rui
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