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    Subject[PATCH v4 RESEND 2/8] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks
    Date
    The IPQ9574 has four PCIe "pipe" clocks. These clocks are required by
    PCIe PHYs. Port the pipe clocks from the downstream 5.4 kernel.

    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
    ---
    drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
    1 file changed, 76 insertions(+)

    diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
    index 0a3f846695b8..bc3e17f34295 100644
    --- a/drivers/clk/qcom/gcc-ipq9574.c
    +++ b/drivers/clk/qcom/gcc-ipq9574.c
    @@ -1569,6 +1569,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
    },
    };

    +static struct clk_branch gcc_pcie0_pipe_clk = {
    + .halt_reg = 0x28044,
    + .halt_check = BRANCH_HALT_DELAY,
    + .clkr = {
    + .enable_reg = 0x28044,
    + .enable_mask = BIT(0),
    + .hw.init = &(const struct clk_init_data) {
    + .name = "gcc_pcie0_pipe_clk",
    + .parent_hws = (const struct clk_hw *[]) {
    + &pcie0_pipe_clk_src.clkr.hw
    + },
    + .num_parents = 1,
    + .flags = CLK_SET_RATE_PARENT,
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
    .reg = 0x29064,
    .clkr = {
    @@ -1583,6 +1601,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
    },
    };

    +static struct clk_branch gcc_pcie1_pipe_clk = {
    + .halt_reg = 0x29044,
    + .halt_check = BRANCH_HALT_DELAY,
    + .clkr = {
    + .enable_reg = 0x29044,
    + .enable_mask = BIT(0),
    + .hw.init = &(const struct clk_init_data) {
    + .name = "gcc_pcie1_pipe_clk",
    + .parent_hws = (const struct clk_hw *[]) {
    + &pcie1_pipe_clk_src.clkr.hw
    + },
    + .num_parents = 1,
    + .flags = CLK_SET_RATE_PARENT,
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
    .reg = 0x2a064,
    .clkr = {
    @@ -1597,6 +1633,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
    },
    };

    +static struct clk_branch gcc_pcie2_pipe_clk = {
    + .halt_reg = 0x2a044,
    + .halt_check = BRANCH_HALT_DELAY,
    + .clkr = {
    + .enable_reg = 0x2a044,
    + .enable_mask = BIT(0),
    + .hw.init = &(const struct clk_init_data) {
    + .name = "gcc_pcie2_pipe_clk",
    + .parent_hws = (const struct clk_hw *[]) {
    + &pcie2_pipe_clk_src.clkr.hw
    + },
    + .num_parents = 1,
    + .flags = CLK_SET_RATE_PARENT,
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
    .reg = 0x2b064,
    .clkr = {
    @@ -1611,6 +1665,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
    },
    };

    +static struct clk_branch gcc_pcie3_pipe_clk = {
    + .halt_reg = 0x2b044,
    + .halt_check = BRANCH_HALT_DELAY,
    + .clkr = {
    + .enable_reg = 0x2b044,
    + .enable_mask = BIT(0),
    + .hw.init = &(const struct clk_init_data) {
    + .name = "gcc_pcie3_pipe_clk",
    + .parent_hws = (const struct clk_hw *[]) {
    + &pcie3_pipe_clk_src.clkr.hw
    + },
    + .num_parents = 1,
    + .flags = CLK_SET_RATE_PARENT,
    + .ops = &clk_branch2_ops,
    + },
    + },
    +};
    +
    static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
    F(24000000, P_XO, 1, 0, 0),
    F(100000000, P_GPLL0, 8, 0, 0),
    @@ -4141,6 +4213,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
    [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
    [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
    [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
    + [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
    + [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
    + [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
    + [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
    };

    static const struct qcom_reset_map gcc_ipq9574_resets[] = {
    --
    2.40.1

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