Messages in this thread Patch in this message | | | From | Dapeng Mi <> | Subject | [PATCH 2/2] perf/x86: Typos and invalid indents fix | Date | Tue, 30 Apr 2024 11:56:53 +0800 |
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Fix several typos and invalid indents.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> --- arch/x86/events/intel/core.c | 2 +- arch/x86/include/asm/perf_event.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 768d1414897f..88c48cd0b625 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3697,7 +3697,7 @@ static void intel_put_event_constraints(struct cpu_hw_events *cpuc, intel_put_shared_regs_event_constraints(cpuc, event); /* - * is PMU has exclusive counter restrictions, then + * If PMU has exclusive counter restrictions, then * all events are subject to and must call the * put_excl_constraints() routine */ diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 3736b8a46c04..9f35ba5216b3 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -399,15 +399,15 @@ static inline bool is_topdown_idx(int idx) * * With this fake counter assigned, the guest LBR event user (such as KVM), * can program the LBR registers on its own, and we don't actually do anything - * with then in the host context. + * with them in the host context. */ -#define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT) +#define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT) /* * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b, * since it would claim bit 58 which is effectively Fixed26. */ -#define INTEL_FIXED_VLBR_EVENT 0x1b00 +#define INTEL_FIXED_VLBR_EVENT 0x1b00 /* * Adaptive PEBS v4 -- 2.40.1
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