Messages in this thread | | | From | Jassi Brar <> | Date | Tue, 30 Apr 2024 21:14:32 -0500 | Subject | Re: [PATCH V4 2/5] mailbox: Add support for QTI CPUCP mailbox controller |
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On Mon, Apr 22, 2024 at 11:41 AM Sibi Sankar <quic_sibis@quicinc.com> wrote: > > Add support for CPUSS Control Processor (CPUCP) mailbox controller, > this driver enables communication between AP and CPUCP by acting as > a doorbell between them. > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > ---
Do you want to add an entry in the MAINTAINERS ?
> diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c ..... > +static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) > +{ > + struct qcom_cpucp_mbox *cpucp = data; > + struct mbox_chan *chan; > + unsigned long flags; > + u64 status; > + u32 val; > + int i; > + The variables flags, val and chan are better inside the for loop below.
> + status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); > + > + for_each_set_bit(i, (unsigned long *)&status, APSS_CPUCP_IPC_CHAN_SUPPORTED) { > + val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); > + chan = &cpucp->chans[i]; > + /* Provide mutual exclusion with changes to chan->cl */ > + spin_lock_irqsave(&chan->lock, flags); > + if (chan->cl) > + mbox_chan_received_data(chan, &val); > + writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); > + spin_unlock_irqrestore(&chan->lock, flags); > + } > + > + return IRQ_HANDLED; > +} > +
Thanks Jassi
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