Messages in this thread | ![/](/images/icornerl.gif) | | Date | Tue, 23 Apr 2024 11:03:26 -0400 | Subject | Re: [PATCH 2/3] phy: zynqmp: Don't wait for PLL lock on nonzero PCIe lanes | From | Sean Anderson <> |
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On 4/23/24 02:25, Michal Simek wrote: > > > On 4/22/24 20:58, Sean Anderson wrote: >> Similarly to DisplayPort, nonzero PCIe lanes never achieve PLL lock [1]. > > What is this [1] for?
I was originally going to have the comment below the fold in the commit message as a footnote. I forgot to remove this after editing.
--Sean
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