Messages in this thread | | | Date | Mon, 22 Apr 2024 08:56:51 +0200 | From | Johan Hovold <> | Subject | Re: [PATCH v21 2/9] usb: dwc3: core: Access XHCI address space temporarily to read port info |
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On Sat, Apr 20, 2024 at 10:18:54AM +0530, Krishna Kurapati wrote: > All DWC3 Multi Port controllers that exist today only support host mode. > Temporarily map XHCI address space for host-only controllers and parse > XHCI Extended Capabilities registers to read number of usb2 ports and > usb3 ports present on multiport controller. Each USB Port is at least HS > capable. > > The port info for usb2 and usb3 phy are identified as num_usb2_ports > and num_usb3_ports and these are used as iterators for phy operations > and for modifying GUSB2PHYCFG/ GUSB3PIPECTL registers accordingly. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
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