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    Subject[PATCH v8 1/7] dt-bindings: spmi: Add X1E80100 SPMI PMIC ARB schema
    Add dedicated schema for X1E80100 PMIC ARB (v7) as it allows multiple
    buses by declaring them as child nodes.

    Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
    Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
    ---
    .../bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml | 136 +++++++++++++++++++++
    1 file changed, 136 insertions(+)

    diff --git a/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml
    new file mode 100644
    index 000000000000..f32a7ae33b4b
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml
    @@ -0,0 +1,136 @@
    +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: Qualcomm X1E80100 SPMI Controller (PMIC Arbiter v7)
    +
    +maintainers:
    + - Stephen Boyd <sboyd@kernel.org>
    +
    +description: |
    + The X1E80100 SPMI PMIC Arbiter implements HW version 7 and it's an SPMI
    + controller with wrapping arbitration logic to allow for multiple on-chip
    + devices to control up to 2 SPMI separate buses.
    +
    + The PMIC Arbiter can also act as an interrupt controller, providing interrupts
    + to slave devices.
    +
    +properties:
    + compatible:
    + const: qcom,x1e80100-spmi-pmic-arb
    +
    + reg:
    + items:
    + - description: core registers
    + - description: tx-channel per virtual slave regosters
    + - description: rx-channel (called observer) per virtual slave registers
    +
    + reg-names:
    + items:
    + - const: core
    + - const: chnls
    + - const: obsrvr
    +
    + ranges: true
    +
    + '#address-cells':
    + const: 2
    +
    + '#size-cells':
    + const: 2
    +
    + qcom,ee:
    + $ref: /schemas/types.yaml#/definitions/uint32
    + minimum: 0
    + maximum: 5
    + description: >
    + indicates the active Execution Environment identifier
    +
    + qcom,channel:
    + $ref: /schemas/types.yaml#/definitions/uint32
    + minimum: 0
    + maximum: 5
    + description: >
    + which of the PMIC Arb provided channels to use for accesses
    +
    +patternProperties:
    + "^spmi@[a-f0-9]+$":
    + type: object
    + $ref: /schemas/spmi/spmi.yaml
    + unevaluatedProperties: false
    +
    + properties:
    + reg:
    + items:
    + - description: configuration registers
    + - description: interrupt controller registers
    +
    + reg-names:
    + items:
    + - const: cnfg
    + - const: intr
    +
    + interrupts:
    + maxItems: 1
    +
    + interrupt-names:
    + const: periph_irq
    +
    + interrupt-controller: true
    +
    + '#interrupt-cells':
    + const: 4
    + description: |
    + cell 1: slave ID for the requested interrupt (0-15)
    + cell 2: peripheral ID for requested interrupt (0-255)
    + cell 3: the requested peripheral interrupt (0-7)
    + cell 4: interrupt flags indicating level-sense information,
    + as defined in dt-bindings/interrupt-controller/irq.h
    +
    +required:
    + - compatible
    + - reg-names
    + - qcom,ee
    + - qcom,channel
    +
    +additionalProperties: false
    +
    +examples:
    + - |
    + #include <dt-bindings/interrupt-controller/arm-gic.h>
    +
    + soc {
    + #address-cells = <2>;
    + #size-cells = <2>;
    +
    + spmi: arbiter@c400000 {
    + compatible = "qcom,x1e80100-spmi-pmic-arb";
    + reg = <0 0x0c400000 0 0x3000>,
    + <0 0x0c500000 0 0x4000000>,
    + <0 0x0c440000 0 0x80000>;
    + reg-names = "core", "chnls", "obsrvr";
    +
    + qcom,ee = <0>;
    + qcom,channel = <0>;
    +
    + #address-cells = <2>;
    + #size-cells = <2>;
    + ranges;
    +
    + spmi_bus0: spmi@c42d000 {
    + reg = <0 0x0c42d000 0 0x4000>,
    + <0 0x0c4c0000 0 0x10000>;
    + reg-names = "cnfg", "intr";
    +
    + interrupt-names = "periph_irq";
    + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-controller;
    + #interrupt-cells = <4>;
    +
    + #address-cells = <2>;
    + #size-cells = <0>;
    + };
    + };
    + };
    --
    2.34.1


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