Messages in this thread | | | Date | Tue, 2 Apr 2024 23:46:29 +0530 | Subject | Re: [PATCH 3/7] clk: qcom: Add DISPCC driver support for SM4450 | From | Ajit Pandey <> |
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On 3/31/2024 6:58 AM, Dmitry Baryshkov wrote: > On Sat, 30 Mar 2024 at 20:29, Ajit Pandey <quic_ajipan@quicinc.com> wrote: >> >> Add Display Clock Controller (DISPCC) support for SM4450 platform. >> >> Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> >> --- >> drivers/clk/qcom/Kconfig | 10 + >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/dispcc-sm4450.c | 781 +++++++++++++++++++++++++++++++ >> 3 files changed, 792 insertions(+) >> create mode 100644 drivers/clk/qcom/dispcc-sm4450.c >> > > [skipped] > >> +static int disp_cc_sm4450_probe(struct platform_device *pdev) >> +{ >> + struct regmap *regmap; > > Is there a MMCX power domain on the platform? See how other dispcc > drivers handle pm_runtime status. > Thanks for review , actually SM4450 doesn't support MMCX power domain pm_rumtime support is not required here. >> + >> + regmap = qcom_cc_map(pdev, &disp_cc_sm4450_desc); >> + if (IS_ERR(regmap)) >> + return PTR_ERR(regmap); >> + >> + clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); >> + clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); >> + >> + /* Keep some clocks always enabled */ >> + qcom_branch_set_clk_en(regmap, 0xe070); /* DISP_CC_SLEEP_CLK */ >> + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ >> + >> + return qcom_cc_really_probe(pdev, &disp_cc_sm4450_desc, regmap); >> +} >> + >> +static struct platform_driver disp_cc_sm4450_driver = { >> + .probe = disp_cc_sm4450_probe, >> + .driver = { >> + .name = "dispcc-sm4450", >> + .of_match_table = disp_cc_sm4450_match_table, >> + }, >> +}; >> + >> +module_platform_driver(disp_cc_sm4450_driver); >> + >> +MODULE_DESCRIPTION("QTI DISPCC SM4450 Driver"); >> +MODULE_LICENSE("GPL"); >> -- >> 2.25.1 >> >> > >
-- Thanks, and Regards Ajit
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