Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Thu, 18 Apr 2024 16:56:49 +0200 | Subject | Re: [PATCH] clk: renesas: r9a07g043: Add clock and reset entry for PLIC |
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Hi Prabhakar,
On Thu, Apr 18, 2024 at 4:53 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Wed, Apr 3, 2024 at 10:11 PM Prabhakar <prabhakar.csengg@gmailcom> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add the missing clock and reset entry for PLIC. Also add > > R9A07G043_NCEPLIC_ACLK to critical clocks list. > > > > Fixes: b3e77da00f1b ("riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC")
That is not the correct commit, I'll replace it by Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") while applying.
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > i.e. will queue in renesas-clk for v6.10.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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