Messages in this thread | | | Subject | Re: [PATCH] peci: aspeed: Clear clock_divider value before setting it | From | Andrew Jeffery <> | Date | Thu, 18 Apr 2024 09:11:47 +0930 |
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Hi Iwona,
On Wed, 2024-04-17 at 15:48 +0200, Iwona Winiarska wrote: > PECI clock divider is programmed on 10:8 bits of PECI Control register. > Before setting a new value, clear bits read from hardware. > > Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
I think it would be best to add a Fixes: tag and Cc: stable in accordance with the stable tree rules. Are you happy to do so?
Andrew
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