Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Wed, 17 Apr 2024 17:04:11 +0200 | Subject | Re: [PATCH v4 5/5] serial: sh-sci: Add support for RZ/V2H(P) SoC |
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On Fri, Mar 22, 2024 at 3:45 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add serial support for RZ/V2H(P) SoC with earlycon. > > The SCIF interface in the Renesas RZ/V2H(P) is similar to that available > in the RZ/G2L (R9A07G044) SoC, with the following differences: > > - RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready > and two for Rx and Tx buffer full, all of which are edge-triggered. > - RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both > synchronous and asynchronous modes. > - There are differences in the configuration of certain registers such > as SCSMR, SCFCR, and SCSPTR between the two SoCs. > > To handle these differences on RZ/V2H(P) SoC SCIx_RZV2H_SCIF_REGTYPE > is added. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > Hi Geert, > > To keep the changes minimal I've added a new regtype instead of > port type. > > Cheers, Prabhakar > > v3 - > v4 > - Added SCIx_RZV2H_SCIF_REGTYPE to handle the differences on the > RZ/V2H(P) SoC
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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