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    Subject[PATCH V3 1/5] dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings
    Date
    Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox
    controller.

    Reviewed-by: Rob Herring <robh@kernel.org>
    Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
    ---

    v2:
    * Pickup Rb from Dimitry.

    .../bindings/mailbox/qcom,cpucp-mbox.yaml | 49 +++++++++++++++++++
    1 file changed, 49 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml

    diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
    new file mode 100644
    index 000000000000..491b0a05e630
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
    @@ -0,0 +1,49 @@
    +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
    +
    +maintainers:
    + - Sibi Sankar <quic_sibis@qti.qualcomm.com>
    +
    +description:
    + The CPUSS Control Processor (CPUCP) mailbox controller enables communication
    + between AP and CPUCP by acting as a doorbell between them.
    +
    +properties:
    + compatible:
    + items:
    + - const: qcom,x1e80100-cpucp-mbox
    +
    + reg:
    + items:
    + - description: CPUCP rx register region
    + - description: CPUCP tx register region
    +
    + interrupts:
    + maxItems: 1
    +
    + "#mbox-cells":
    + const: 1
    +
    +required:
    + - compatible
    + - reg
    + - interrupts
    + - "#mbox-cells"
    +
    +additionalProperties: false
    +
    +examples:
    + - |
    + #include <dt-bindings/interrupt-controller/arm-gic.h>
    +
    + mailbox@17430000 {
    + compatible = "qcom,x1e80100-cpucp-mbox";
    + reg = <0x17430000 0x10000>, <0x18830000 0x10000>;
    + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
    + #mbox-cells = <1>;
    + };
    --
    2.34.1

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