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SubjectRe: [PATCH 4/5] arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes
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On 4/16/24 22:00, Dmitry Baryshkov wrote:
> On Thu, 28 Mar 2024 at 11:52, Sibi Sankar <quic_sibis@quicinc.com> wrote:
>>
>> Add the cpucp mailbox and sram nodes required by SCMI perf protocol
>> on X1E80100 SoCs.
>>
>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 26 ++++++++++++++++++++++++++
>> 1 file changed, 26 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index 28f65296781d..4e0ec859ed61 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -4974,6 +4974,13 @@ gic_its: msi-controller@17040000 {
>> };
>> };
>>
>> + cpucp_mbox: mailbox@17430000 {
>> + compatible = "qcom,x1e80100-cpucp-mbox";
>> + reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>;
>> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
>> + #mbox-cells = <1>;
>> + };
>> +
>> apps_rsc: rsc@17500000 {
>> compatible = "qcom,rpmh-rsc";
>> reg = <0 0x17500000 0 0x10000>,
>> @@ -5157,6 +5164,25 @@ frame@1780d000 {
>> };
>> };
>>
>> + sram: sram@18b4e000 {
>> + compatible = "mmio-sram";
>> + reg = <0x0 0x18b4e000 0x0 0x400>;
>> + ranges = <0x0 0x0 0x18b4e000 0x400>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + cpu_scp_lpri0: scmi-shmem@0 {
>
> This doesn't seem to follow the schema.

ack, will rename the nodes in the next re-spin.

-Sibi

>
>> + compatible = "arm,scmi-shmem";
>> + reg = <0x0 0x200>;
>> + };
>> +
>> + cpu_scp_lpri1: scmi-shmem@200 {
>> + compatible = "arm,scmi-shmem";
>> + reg = <0x200 0x200>;
>> + };
>> + };
>> +
>> system-cache-controller@25000000 {
>> compatible = "qcom,x1e80100-llcc";
>> reg = <0 0x25000000 0 0x200000>,
>> --
>> 2.34.1
>>
>>
>
>

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