Messages in this thread | | | Date | Wed, 17 Apr 2024 07:53:04 +0800 | Subject | Re: [PATCH 2/3] mmc: sdhci-of-dwcmshc: Add support for Sophgo SG2042 | From | Chen Wang <> |
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On 2024/4/16 23:37, Jisheng Zhang wrote: > On Tue, Apr 16, 2024 at 05:50:57PM +0800, Chen Wang wrote: [......] >> >> +#define SG2042_MAX_CLKS 2 > I don't think "bulk" is suitable here for max 2 clks, no? Without "bulk", I have to prepare/disable two times for each of clocks and handle the exception if first one failed etc. I learn this from rockchip, it has 3. Why you think it is not suitable, please advise me, thanks. >> +struct sg2042_priv { >> + struct clk_bulk_data clks[SG2042_MAX_CLKS]; > useless either
Sorry, what's this mean?
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>> + >> + /* Set ATDL_CNFG, tuning clk not use for init */ >> + val = FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, 2); > magic "2" needs a meaningful macro definition.
Agree, will improve this in next version.
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>> >> +static const struct sdhci_pltfm_data sdhci_dwcmshc_sg2042_pdata = { >> + .ops = &sdhci_dwcmshc_sg2042_ops, >> + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | >> + SDHCI_QUIRK_INVERTED_WRITE_PROTECT, > is "wp-inverted" property better?
Yes, l will use this in next revision, thanks.
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>> + >> +static int dwcmshc_sg2042_init(struct device *dev, >> + struct sdhci_host *host, >> + struct dwcmshc_priv *dwc_priv) >> +{ >> + int err; >> + struct sg2042_priv *soc = NULL; >> + >> + soc = devm_kzalloc(dev, sizeof(struct sg2042_priv), GFP_KERNEL); >> + if (!soc) >> + return -ENOMEM; >> + >> + soc->clks[0].id = "card"; >> + soc->clks[1].id = "timer"; > Interesting, only "card" and "timer", so which clk is for clk input of the ip?
Copy my comments from bindings patch here for quick reference:
> SG2042 defines 3 clocks for SD/eMMC controllers.
>- AXI_EMMC/AXI_SD for aclk/hclk(Bus interface clocks in DWC_mshc) > and bclk(Core Base Clock in DWC_mshc), these 3 clocks share one > source, so reuse existing "core". >- 100K_EMMC/100K_SD for cqetmclk(Timer clocks in DWC_mshc), so reuse > existing "timer" which was added for rockchip specified.
>- EMMC_100M/SD_100M for cclk(Card clocks in DWC_mshc), add new "card".
What you meant "clk input of the ip" is "core", right?
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