Messages in this thread | | | Date | Sat, 13 Apr 2024 10:10:40 +0800 | Subject | Re: [RFC PATCH 15/41] KVM: x86/pmu: Manage MSR interception for IA32_PERF_GLOBAL_CTRL | From | "Mi, Dapeng" <> |
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On 4/12/2024 6:30 AM, Jim Mattson wrote: > On Thu, Apr 11, 2024 at 2:21 PM Sean Christopherson <seanjc@google.com> wrote: >> On Fri, Jan 26, 2024, Xiong Zhang wrote: >>> + if (is_passthrough_pmu_enabled(&vmx->vcpu)) { >>> + /* >>> + * Setup auto restore guest PERF_GLOBAL_CTRL MSR at vm entry. >>> + */ >>> + if (vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) >>> + vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, 0); >>> + else { >>> + i = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, >>> + MSR_CORE_PERF_GLOBAL_CTRL); >>> + if (i < 0) { >>> + i = vmx->msr_autoload.guest.nr++; >>> + vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, >>> + vmx->msr_autoload.guest.nr); >>> + } >>> + vmx->msr_autoload.guest.val[i].index = MSR_CORE_PERF_GLOBAL_CTRL; >>> + vmx->msr_autoload.guest.val[i].value = 0; >> Eww, no. Just make cpu_has_load_perf_global_ctrl() and VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL >> hard requirements for enabling passthrough mode. And then have clear_atomic_switch_msr() >> yell if KVM tries to disable loading MSR_CORE_PERF_GLOBAL_CTRL. > Weren't you just complaining about the PMU version 4 constraint in > another patch? And here, you are saying, "Don't support anything older > than Sapphire Rapids." > > Sapphire Rapids has PMU version 4, so if we require > VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, PMU version 4 is irrelevant.
Just clarify Sapphire Rapids has PMU version 5 :).
[ 2.687826] Performance Events: XSAVE Architectural LBR, PEBS fmt4+-baseline, AnyThread deprecated, *Sapphire Rapids events*, 32-deep LBR, full-width counters, Intel PMU driver. [ 2.687925] ... version: 5 [ 2.687928] ... bit width: 48 [ 2.687929] ... generic counters: 8
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