Messages in this thread | ![/](/images/icornerl.gif) | | From | Yangyu Chen <> | Subject | Re: [PATCH] perf: RISC-V: fix IRQ detection on T-Head C908 | Date | Fri, 12 Apr 2024 14:27:28 +0800 |
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>> IMHO, it may be better to use a new DT property like "riscv,cpu-errata" or >> "<vendor>,cpu-errata". It can achieve almost everything like using pseudo >> isa. And the only cost I think is a small amount code to parse this. > > I suppose we could do that, but accounting for vendor specifics was one > of the goals for the property I only just added and that I am suggesting > to use here.
I think there is a simpler way to do that. We use T-Head PMU by default for All T-Head CPUs (from mvendor id). Then, to test there is sscofpmf in the ISA string being probed by the kernel. If yes, then use scofpmf. Otherwise, use T-Head PMU.
I will check if this can also be switched in any vendor CSR like Svpbmt and T-Head MAE we discussed before.
Thanks, Yangyu Chen
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