Messages in this thread | | | Date | Wed, 10 Apr 2024 18:32:53 +0200 | From | Neil Armstrong <> | Subject | Re: [PATCH 2/4] clk: qcom: dispcc-sm6350: fix DisplayPort clocks |
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On 08/04/2024 13:47, Dmitry Baryshkov wrote: > On SM6350 DisplayPort link clocks use frequency tables inherited from > the vendor kernel, it is not applicable in the upstream kernel. Drop > frequency tables and use clk_byte2_ops for those clocks. > > Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/clk/qcom/dispcc-sm6350.c | 11 +---------- > 1 file changed, 1 insertion(+), 10 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c > index 839435362010..e4b7464c4d0e 100644 > --- a/drivers/clk/qcom/dispcc-sm6350.c > +++ b/drivers/clk/qcom/dispcc-sm6350.c > @@ -221,26 +221,17 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { > }, > }; > > -static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { > - F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - { } > -}; > - > static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { > .cmd_rcgr = 0x10f8, > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_0, > - .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, > .clkr.hw.init = &(struct clk_init_data){ > .name = "disp_cc_mdss_dp_link_clk_src", > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > >
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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