Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Thu, 14 Mar 2024 16:59:57 +0100 | Subject | Re: [PATCH v2 06/10] clk: renesas: rzg2l: Extend power domain support |
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Hi Claudiu,
On Thu, Mar 7, 2024 at 3:07 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra > power when clocks are disabled by activating module standby. This is done > through MSTOP-specific registers that are part of CPG. Each individual > module has one or more bits associated with one MSTOP register (see table > "Registers for Module Standby Mode" from HW manuals). Hardware manual > associates modules' clocks with one or more MSTOP bits. There are 3 > mappings available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW > manuals): > > case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X}) > case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X}) > case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, .., Y}) > > Case 3 has been currently identified on RZ/V2L for the VCPL4 module. > > To cover all three cases, the individual platform drivers will provide to > clock driver MSTOP register offset and associated bits in this register > as a bitmask and the clock driver will apply this bitmask to proper > MSTOP register. > > Apart from MSTOP support, RZ/G3S can save more power by powering down the > individual IPs (after MSTOP has been set) if proper bits in > CPG_PWRDN_IP{1,2} registers are set. > > The MSTOP and IP power down support were implemented through power > domains. Platform-specific clock drivers will register an array of > type struct rzg2l_cpg_pm_domain_init_data, which will be used to > instantiate properly the power domains. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v2: > - called pm_genpd_init() with proper value for is_off argument > - fixed typos > - used flexible array for struct rzg2l_cpg_pm_domains::domains member > - moved genpd member of struct rzg2l_cpg_pd at the beginning of struct > - didn't initialize the parent variable in rzg2l_cpg_add_pm_domains() > as it is already initialized in the for block from > rzg2l_cpg_add_pm_domains() and that initialization should be enough > - dropped RZG2L_PD_F_PARENT flag > - used datasheet naming for all MSTOP registers > - added all MSTOP registers to rzg2l-cpg.h > - reworked the code that initializes the register offset and bits for domains > - dropped MSTOP*(), PWRDN*() macros and introduced struct rzg2l_cpg_reg_conf > and DEF_REG_CONF() for domain description > - constified the 1st argument of rzg2l_cpg_pm_domain_xlate() > - used dev instead of priv->dev where possible > - dropped RZG2L_PD_F_PARENT > - added RZG2L_PD_F_NONE for better description of domains in platform > specific clock drivers
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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