Messages in this thread Patch in this message | | | From | Manivannan Sadhasivam <> | Date | Wed, 24 Jan 2024 13:06:40 +0530 | Subject | [PATCH 12/14] arm64: dts: qcom: sm8550: Drop PCIE_AUX_CLK from pcie_phy node |
| |
PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy node.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee1ba5a8c8fc..f074683f7940 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1760,13 +1760,11 @@ pcie0_phy: phy@1c06000 { compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; reg = <0 0x01c06000 0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&tcsr TCSR_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", - "pipe"; + clock-names = "cfg_ahb", "ref", "rchng", "pipe"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; -- 2.25.1
| |