Messages in this thread | | | Date | Wed, 10 Jan 2024 17:00:30 +0100 | Subject | Re: [PATCH] i2c: cadence: Avoid fifo clear after start | From | Michal Simek <> |
| |
On 1/5/24 13:52, Sai Pavan Boddu wrote: > Driver unintentionally programs ctrl reg to clear fifo which is > happening after start of transaction, this was not the case previously > as it was read-modified-write. This issue breaks i2c reads on QEMU as > i2c-read is done before guest starts programming ctrl register. > > Fixes: ff0cf7bca6309 ("i2c: cadence: Remove unnecessary register reads") > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> > --- > drivers/i2c/busses/i2c-cadence.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c > index de3f58b60dce..6f7d753a8197 100644 > --- a/drivers/i2c/busses/i2c-cadence.c > +++ b/drivers/i2c/busses/i2c-cadence.c > @@ -633,6 +633,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id) > > if (hold_clear) { > ctrl_reg &= ~CDNS_I2C_CR_HOLD; > + ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO; > /* > * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size > * register reaches '0'. This is an IP bug which causes transfer size
Acked-by: Michal Simek <michal.simek@amd.com>
Thanks, Michal
| |