Messages in this thread | ![/](/images/icornerl.gif) | | Date | Tue, 6 Jun 2023 15:53:51 +0300 | Subject | Re: [PATCH v1] meson saradc: fix clock divider mask length | From | George Stark <> |
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On 6/5/23 23:18, Martin Blumenstingl wrote: > Hi George, > > On Thu, Jun 1, 2023 at 10:56 PM George Stark <gnstark@sberdevices.ru> wrote: > [...] >> Here the test I promised: >> Question: what's the real size of clock divder field in SAR_ADC_REG3 register in saradc in meson8 socs? >> The current kernel code says 5 bits >> The datasheet says 6 bit >> >> The parent clock of adc clock is 24Mhz >> I can check it here by: >> >> # cat /sys/kernel/debug/clk/clk_summary >> xtal 4 4 1 24000000 0 0 50000 Y >> c1108680.adc#adc_div 1 1 0 1142858 0 0 50000 Y >> c1108680.adc#adc_en 1 1 0 1142858 0 0 50000 Y >> >> for divider width 5bit min adc clock is 24Mhz / 32 = 750KHZ >> for divider width 6bit min adc clock is 24Mhz / 64 = 375KHz >> >> I suppose that the lower adc clock rate the higher measurement time >> so I need to get measurement time at both clk freqs and the times differ so >> 6bit divider is really applied >> >> I performed test at Odroid-C1, kernel 6.2-rc8 >> Two kernel patches must be applied: >> >> the topic starter patch and the helper patch at the end of the letter >> In the helper patch I turn on CLOCK_ALLOW_WRITE_DEBUGFS to change clock rate from she shell >> and use ktime_get_raw_ts64 to measure measurement time >> >> So the the test itself: >> cat /sys/devices/platform/soc/c1100000.cbus/c1108680.adc/iio:device0/in_voltage3_raw >> [ 1781.226309] ==== freq: 1142858 time 42408000 >> >> # echo 750000 > /sys/kernel/debug/clk/c1108680.adc#adc_en/clk_rate >> # cat /sys/devices/platform/soc/c1100000.cbus/c1108680.adc/iio:device0/in_voltage3_raw >> [ 1790.728656] ==== freq: 750000 time 49173000 >> >> # echo 375000 > /sys/kernel/debug/clk/c1108680.adc#adc_en/clk_rate >> # cat /sys/devices/platform/soc/c1100000.cbus/c1108680.adc/iio:device0/in_voltage3_raw >> [ 1816.955477] ==== freq: 375000 time 68245000 >> >> # cat /sys/kernel/debug/clk/clk_summary >> xtal 4 4 1 24000000 0 0 50000 Y >> c1108680.adc#adc_div 1 1 0 375000 0 0 50000 Y >> c1108680.adc#adc_en 1 1 0 375000 0 0 50000 Y > These results looks excellent - thanks for sharing the test results! > Could you please check one last thing: > $ grep -i adc /sys/kernel/debug/meson-clk-msr/measure_summary > It should confirm that the clock rate is 375kHz (or close to it, SoC > internal clock measurement is not 100% precise) Hello Martin
Looks like it works as expected: # grep -i adc /sys/kernel/debug/meson-clk-msr/measure_summary sar_adc 1140625 +/-3125Hz # echo 375000 > /sys/kernel/debug/clk/c1108680.adc#adc_en/clk_rate # grep -i adc /sys/kernel/debug/meson-clk-msr/measure_summary sar_adc 371875 +/-3125Hz
So I'm re-sending the patch with fixed commit message
-- Best regards George
> > Once we have that confirmation: can you please re-send the patch with > the description updated so it's clear which SoC generations are > affected and by stating that the fix was tested on a Meson8b Odroid-C1 > board. > > > Thank you and best regards, > Martin
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