Messages in this thread | ![/](/images/icornerl.gif) | | Date | Mon, 5 Jun 2023 09:37:21 +0200 | From | Simon Horman <> | Subject | Re: [PATCH net-next v4 1/4] net: mdio: Introduce a regmap-based mdio driver |
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On Thu, Jun 01, 2023 at 04:14:51PM +0200, Maxime Chevallier wrote: > There exists several examples today of devices that embed an ethernet > PHY or PCS directly inside an SoC. In this situation, either the device > is controlled through a vendor-specific register set, or sometimes > exposes the standard 802.3 registers that are typically accessed over > MDIO. > > As phylib and phylink are designed to use mdiodevices, this driver > allows creating a virtual MDIO bus, that translates mdiodev register > accesses to regmap accesses. > > The reason we use regmap is because there are at least 3 such devices > known today, 2 of them are Altera TSE PCS's, memory-mapped, exposed > with a 4-byte stride in stmmac's dwmac-socfpga variant, and a 2-byte > stride in altera-tse. The other one (nxp,sja1110-base-tx-mdio) is > exposed over SPI. > > Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: Simon Horman <simon.horman@corigine.com>
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