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    SubjectRE: [PATCH v5 11/26] cxl/pci: Early setup RCH dport component registers from RCRB
    Terry Bowman wrote:
    > From: Robert Richter <rrichter@amd.com>
    >
    > CXL RAS capabilities must be enabled and accessible as soon as the CXL
    > endpoint is detected in the PCI hierarchy and bound to the cxl_pci
    > driver. This needs to be independent of other modules such as cxl_port
    > or cxl_mem.
    >
    > CXL RAS capabilities reside in the Component Registers. For an RCH
    > this is determined by probing RCRB which is implemented very late once
    > the CXL Memory Device is created.
    >
    > Change this by moving the RCRB probe to the cxl_pci driver. Do this by
    > using a new introduced function cxl_pci_find_port() similar to
    > cxl_mem_find_port() to determine the involved dport by the endpoint's
    > PCI handle. Plug this into the existing cxl_pci_setup_regs() function
    > to setup Component Registers. Probe the RCRB in case the Component
    > Registers cannot be located through the CXL Register Locator
    > capability.
    >
    > This unifies code and early sets up the Component Registers at the
    > same time for both, VH and RCH mode. Only the cxl_pci driver is
    > involved for this. This allows an early mapping of the CXL RAS
    > capability registers.
    >
    > Signed-off-by: Robert Richter <rrichter@amd.com>
    > Signed-off-by: Terry Bowman <terry.bowman@amd.com>
    > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    [..]
    > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
    > index 945ca0304d68..2975b232fcd1 100644
    > --- a/drivers/cxl/pci.c
    > +++ b/drivers/cxl/pci.c
    > @@ -274,13 +274,48 @@ static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds)
    > return 0;
    > }
    >
    > +/* Extract RCRB, use same function interface as cxl_find_regblock(). */
    > +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
    > + enum cxl_regloc_type type,
    > + struct cxl_register_map *map)
    > +{
    > + struct cxl_dport *dport;
    > + resource_size_t component_reg_phys;
    > +
    > + memset(map, 0, sizeof(*map));
    > + map->dev = &pdev->dev;
    > + map->resource = CXL_RESOURCE_NONE;
    > +
    > + if (type != CXL_REGLOC_RBI_COMPONENT)
    > + return -ENODEV;
    > +
    > + if (!cxl_pci_find_port(pdev, &dport) || !dport->rch)
    > + return -ENXIO;

    I noticed while reviewing a later patch that this pattern leaks the port
    reference from cxl_pci_find_port().

    I.e. this needs to do:

    port = cxl_pci_find_port(...);
    if (!port)
    return -ENXIO;
    if (!dport->rch)
    goto out;
    ...
    out:
    put_device(&port->dev);

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