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    Subject[PATCH AUTOSEL 6.3 42/67] ARM: dts: stm32: add CAN support on stm32f746
    Date
    From: Dario Binacchi <dario.binacchi@amarulasolutions.com>

    [ Upstream commit 0920ccdf41e3078a4dd2567eb905ea154bc826e6 ]

    Add support for bxcan (Basic eXtended CAN controller) to STM32F746. The
    chip contains three CAN peripherals, CAN1 and CAN2 in dual peripheral
    configuration and CAN3 in single peripheral configuration:
    - Dual CAN peripheral configuration:
    * CAN1: Primary bxCAN for managing the communication between a secondary
    bxCAN and the 512-byte SRAM memory.
    * CAN2: Secondary bxCAN with no direct access to the SRAM memory.
    This means that the two bxCAN cells share the 512-byte SRAM memory and
    CAN2 can't be used without enabling CAN1.
    - Single CAN peripheral configuration:
    * CAN3: Primary bxCAN with dedicated Memory Access Controller unit and
    512-byte SRAM memory.

    -------------------------------------------------------------------------
    | features | CAN1 | CAN2 | CAN 3 |
    -------------------------------------------------------------------------
    | SRAM | 512-byte shared between CAN1 & CAN2 | 512-byte |
    -------------------------------------------------------------------------
    | Filters | 26 filters shared between CAN1 & CAN2 | 14 filters |
    -------------------------------------------------------------------------

    Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
    Link: https://lore.kernel.org/all/20230427204540.3126234-6-dario.binacchi@amarulasolutions.com
    Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm/boot/dts/stm32f746.dtsi | 47 ++++++++++++++++++++++++++++++++
    1 file changed, 47 insertions(+)

    diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
    index dc868e6da40e0..973698bc9ef4b 100644
    --- a/arch/arm/boot/dts/stm32f746.dtsi
    +++ b/arch/arm/boot/dts/stm32f746.dtsi
    @@ -257,6 +257,23 @@ rtc: rtc@40002800 {
    status = "disabled";
    };

    + can3: can@40003400 {
    + compatible = "st,stm32f4-bxcan";
    + reg = <0x40003400 0x200>;
    + interrupts = <104>, <105>, <106>, <107>;
    + interrupt-names = "tx", "rx0", "rx1", "sce";
    + resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
    + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
    + st,gcan = <&gcan3>;
    + status = "disabled";
    + };
    +
    + gcan3: gcan@40003600 {
    + compatible = "st,stm32f4-gcan", "syscon";
    + reg = <0x40003600 0x200>;
    + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
    + };
    +
    usart2: serial@40004400 {
    compatible = "st,stm32f7-uart";
    reg = <0x40004400 0x400>;
    @@ -337,6 +354,36 @@ i2c4: i2c@40006000 {
    status = "disabled";
    };

    + can1: can@40006400 {
    + compatible = "st,stm32f4-bxcan";
    + reg = <0x40006400 0x200>;
    + interrupts = <19>, <20>, <21>, <22>;
    + interrupt-names = "tx", "rx0", "rx1", "sce";
    + resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
    + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
    + st,can-primary;
    + st,gcan = <&gcan1>;
    + status = "disabled";
    + };
    +
    + gcan1: gcan@40006600 {
    + compatible = "st,stm32f4-gcan", "syscon";
    + reg = <0x40006600 0x200>;
    + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
    + };
    +
    + can2: can@40006800 {
    + compatible = "st,stm32f4-bxcan";
    + reg = <0x40006800 0x200>;
    + interrupts = <63>, <64>, <65>, <66>;
    + interrupt-names = "tx", "rx0", "rx1", "sce";
    + resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
    + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
    + st,can-secondary;
    + st,gcan = <&gcan1>;
    + status = "disabled";
    + };
    +
    cec: cec@40006c00 {
    compatible = "st,stm32-cec";
    reg = <0x40006C00 0x400>;
    --
    2.39.2
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