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    Subject[PATCH 3/3] phy: ti: gmii-sel: Enable SGMII mode for J721E
    Date
    TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW
    Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
    corresponding extra_modes member.

    Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
    ---
    drivers/phy/ti/phy-gmii-sel.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
    index b0335a8abc18..fd934a38b71d 100644
    --- a/drivers/phy/ti/phy-gmii-sel.c
    +++ b/drivers/phy/ti/phy-gmii-sel.c
    @@ -228,7 +228,7 @@ static const
    struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
    .use_of_data = true,
    .regfields = phy_gmii_sel_fields_am654,
    - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
    + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
    .num_ports = 8,
    .num_qsgmii_main_ports = 2,
    };
    --
    2.25.1
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