Messages in this thread Patch in this message | | | From | Nicolin Chen <> | Subject | [PATCH v1 02/14] iommufd: Add nesting related data structures for ARM SMMUv3 | Date | Thu, 9 Mar 2023 02:53:38 -0800 |
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Add the following data structures for corresponding ioctls: iommu_hwpt_arm_smmuv3 => IOMMUFD_CMD_HWPT_ALLOC iommu_hwpt_invalidate_arm_smmuv3 => IOMMUFD_CMD_HWPT_INVALIDATE
Also, add IOMMU_HW_INFO_TYPE_ARM_SMMUV3 and IOMMU_PGTBL_TYPE_ARM_SMMUV3_S1 to the header and corresponding type/size arrays.
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> --- drivers/iommu/iommufd/hw_pagetable.c | 4 +++ drivers/iommu/iommufd/main.c | 1 + include/uapi/linux/iommufd.h | 50 ++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+)
diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/hw_pagetable.c index 8f9985bddeeb..5e798b2f9a3a 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -173,6 +173,7 @@ iommufd_hw_pagetable_alloc(struct iommufd_ctx *ictx, struct iommufd_ioas *ioas, static const size_t iommufd_hwpt_alloc_data_size[] = { [IOMMU_HWPT_TYPE_DEFAULT] = 0, [IOMMU_HWPT_TYPE_VTD_S1] = sizeof(struct iommu_hwpt_intel_vtd), + [IOMMU_HWPT_TYPE_ARM_SMMUV3] = sizeof(struct iommu_hwpt_arm_smmuv3), }; /* @@ -183,6 +184,8 @@ const u64 iommufd_hwpt_type_bitmaps[] = { [IOMMU_HW_INFO_TYPE_DEFAULT] = BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT), [IOMMU_HW_INFO_TYPE_INTEL_VTD] = BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT) | BIT_ULL(IOMMU_HWPT_TYPE_VTD_S1), + [IOMMU_HW_INFO_TYPE_ARM_SMMUV3] = BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT) | + BIT_ULL(IOMMU_HWPT_TYPE_ARM_SMMUV3), }; /* Return true if type is supported, otherwise false */ @@ -329,6 +332,7 @@ int iommufd_hwpt_alloc(struct iommufd_ucmd *ucmd) */ static const size_t iommufd_hwpt_invalidate_info_size[] = { [IOMMU_HWPT_TYPE_VTD_S1] = sizeof(struct iommu_hwpt_invalidate_intel_vtd), + [IOMMU_HWPT_TYPE_ARM_SMMUV3] = sizeof(struct iommu_hwpt_invalidate_arm_smmuv3), }; int iommufd_hwpt_invalidate(struct iommufd_ucmd *ucmd) diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 514db4c26927..0b0097af7c86 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -280,6 +280,7 @@ union ucmd_buffer { * path. */ struct iommu_hwpt_invalidate_intel_vtd vtd; + struct iommu_hwpt_invalidate_arm_smmuv3 smmuv3; }; struct iommufd_ioctl_op { diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 2a6c326391b2..0d5551b1b2be 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -352,10 +352,13 @@ struct iommu_vfio_ioas { * enum iommu_hwpt_type - IOMMU HWPT Type * @IOMMU_HWPT_TYPE_DEFAULT: default * @IOMMU_HWPT_TYPE_VTD_S1: Intel VT-d stage-1 page table + * @IOMMU_HWPT_TYPE_ARM_SMMUV3: ARM SMMUv3 stage-1 Context Descriptor + * table */ enum iommu_hwpt_type { IOMMU_HWPT_TYPE_DEFAULT, IOMMU_HWPT_TYPE_VTD_S1, + IOMMU_HWPT_TYPE_ARM_SMMUV3, }; /** @@ -411,6 +414,28 @@ struct iommu_hwpt_intel_vtd { __u32 __reserved; }; +/** + * struct iommu_hwpt_arm_smmuv3 - ARM SMMUv3 specific page table data + * + * @flags: page table entry attributes + * @s2vmid: Virtual machine identifier + * @s1ctxptr: Stage-1 context descriptor pointer + * @s1cdmax: Number of CDs pointed to by s1ContextPtr + * @s1fmt: Stage-1 Format + * @s1dss: Default substream + */ +struct iommu_hwpt_arm_smmuv3 { +#define IOMMU_SMMUV3_FLAG_S2 (1 << 0) /* if unset, stage-1 */ +#define IOMMU_SMMUV3_FLAG_VMID (1 << 1) /* vmid override */ + __u64 flags; + __u32 s2vmid; + __u32 __reserved; + __u64 s1ctxptr; + __u64 s1cdmax; + __u64 s1fmt; + __u64 s1dss; +}; + /** * struct iommu_hwpt_alloc - ioctl(IOMMU_HWPT_ALLOC) * @size: sizeof(struct iommu_hwpt_alloc) @@ -446,6 +471,8 @@ struct iommu_hwpt_intel_vtd { * +------------------------------+-------------------------------------+-----------+ * | IOMMU_HWPT_TYPE_VTD_S1 | struct iommu_hwpt_intel_vtd | HWPT | * +------------------------------+-------------------------------------+-----------+ + * | IOMMU_HWPT_TYPE_ARM_SMMUV3 | struct iommu_hwpt_arm_smmuv3 | IOAS/HWPT | + * +------------------------------+-------------------------------------------------+ */ struct iommu_hwpt_alloc { __u32 size; @@ -463,10 +490,12 @@ struct iommu_hwpt_alloc { /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type + * @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type */ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_DEFAULT, IOMMU_HW_INFO_TYPE_INTEL_VTD, + IOMMU_HW_INFO_TYPE_ARM_SMMUV3, }; /** @@ -591,6 +620,25 @@ struct iommu_hwpt_invalidate_intel_vtd { __u64 nb_granules; }; +/** + * struct iommu_hwpt_invalidate_arm_smmuv3 - ARM SMMUv3 cahce invalidation info + * @flags: boolean attributes of cache invalidation command + * @opcode: opcode of cache invalidation command + * @ssid: SubStream ID + * @granule_size: page/block size of the mapping in bytes + * @range: IOVA range to invalidate + */ +struct iommu_hwpt_invalidate_arm_smmuv3 { +#define IOMMU_SMMUV3_CMDQ_TLBI_VA_LEAF (1 << 0) + __u64 flags; + __u8 opcode; + __u8 padding[3]; + __u32 asid; + __u32 ssid; + __u32 granule_size; + struct iommu_iova_range range; +}; + /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate) @@ -609,6 +657,8 @@ struct iommu_hwpt_invalidate_intel_vtd { * +------------------------------+----------------------------------------+ * | IOMMU_HWPT_TYPE_VTD_S1 | struct iommu_hwpt_invalidate_intel_vtd | * +------------------------------+----------------------------------------+ + * | IOMMU_HWPT_TYPE_ARM_SMMUV3 | struct iommu_hwpt_invalidate_arm_smmuv3| + * +------------------------------+----------------------------------------+ */ struct iommu_hwpt_invalidate { __u32 size; -- 2.39.2
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