Messages in this thread Patch in this message | | | Date | Thu, 9 Mar 2023 10:12:24 +0000 | From | Joey Gouly <> | Subject | Re: [PATCH v2] arm64/sysreg: Convert HFG[RW]TR_EL2 to automatic generation |
| |
Hi Mark,
On Tue, Mar 07, 2023 at 07:11:09PM +0000, Mark Brown wrote: > Convert the fine grained traps read and write control registers to > automatic generation as per DDI0601 2022-12. No functional changes. > > Signed-off-by: Mark Brown <broonie@kernel.org> > --- > Changes in v2: > - Correct naming of nPIRE0_EL1. > - Link to v1: https://lore.kernel.org/r/20230306-arm64-fgt-reg-gen-v1-1-95bc0c97cfed@kernel.org > --- > arch/arm64/include/asm/sysreg.h | 8 ----- > arch/arm64/tools/sysreg | 75 +++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 75 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 9e3ecba3c4e6..e5ca9ece1606 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -419,8 +419,6 @@ > #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) > #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) > #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3) > -#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4) > -#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5) > #define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6) > #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7) > > @@ -758,12 +756,6 @@ > #define ICH_VTR_TDS_SHIFT 19 > #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT) > > -/* HFG[WR]TR_EL2 bit definitions */ > -#define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55 > -#define HFGxTR_EL2_nTPIDR2_EL0_MASK BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT) > -#define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54 > -#define HFGxTR_EL2_nSMPRI_EL1_MASK BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT) > - > #define ARM64_FEATURE_FIELD_BITS 4 > > /* Defined for compatibility only, do not add new users. */ > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index dd5a9c7e310f..60829a9409f0 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -1866,6 +1866,81 @@ Field 1 ZA > Field 0 SM > EndSysreg > > +SysregFields HFGxTR_EL2 > +Field 63 nAMIAIR2_EL1 > +Field 62 nMAIR2_EL1 > +Field 61 nS2POR_EL1 > +Field 60 nPOR_EL1 > +Field 59 nPOR_EL0 > +Field 58 nPIR_EL1 > +Field 57 nPIRE0_EL1 > +Field 56 nRCWMASK_EL1 > +Field 55 nTPIDR2_EL0 > +Field 54 nSMPRI_EL1 > +Field 53 nGCS_EL1 > +Field 52 nGCS_EL0 > +Res0 51 > +Field 50 nACCDATA_EL1 > +Field 49 ERXADDR_EL1 > +Field 48 EXRPFGCDN_EL1 > +Field 47 EXPFGCTL_EL1 > +Field 46 EXPFGF_EL1 > +Field 45 ERXMISCn_EL1 > +Field 44 ERXSTATUS_EL1 > +Field 43 ERXCTLR_EL1 > +Field 42 ERXFR_EL1 > +Field 41 ERRSELR_EL1 > +Field 40 ERRIDR_EL1 > +Field 39 ICC_IGRPENn_EL1 > +Field 38 VBAR_EL1 > +Field 37 TTBR1_EL1 > +Field 36 TTBR0_EL1 > +Field 35 TPIDR_EL0 > +Field 34 TPIDRRO_EL0 > +Field 33 TPIDR_EL1 > +Field 32 TCR_EL1 > +Field 31 SCTXNUM_EL0 > +Field 30 SCTXNUM_EL1 > +Field 29 SCTLR_EL1 > +Field 28 REVIDR_EL1 > +Field 27 PAR_EL1 > +Field 26 MPIDR_EL1 > +Field 25 MIDR_EL1 > +Field 24 MAIR_EL1 > +Field 23 LORSA_EL1 > +Field 22 LORN_EL1 > +Field 21 LORID_EL1 > +Field 20 LOREA_EL1 > +Field 19 LORC_EL1 > +Field 18 ISR_EL1 > +Field 17 FAR_EL1 > +Field 16 ESR_EL1 > +Field 15 DCZID_EL0 > +Field 14 CTR_EL0 > +Field 13 CSSELR_EL1 > +Field 12 CPACR_EL1 > +Field 11 CONTEXTIDR_EL1 > +Field 10 CLIDR_EL1 > +Field 9 CCSIDR_EL1 > +Field 8 APIBKey > +Field 7 APIAKey > +Field 6 APGAKey > +Field 5 APDBKey > +Field 4 APDAKey > +Field 3 AMAIR_EL1 > +Field 2 AIDR_EL1 > +Field 1 AFSR1_EL1 > +Field 0 AFSR0_EL1 > +EndSysregFields > + > +Sysreg HFGRTR_EL2 3 4 1 1 4 > +Fields HFGxTR_EL2 > +EndSysreg > + > +Sysreg HFGWTR_EL2 3 4 1 1 5 > +Fields HFGxTR_EL2 > +EndSysreg > + > Sysreg ZCR_EL2 3 4 1 2 0 > Fields ZCR_ELx > EndSysreg >
Reviewed-by: Joey Gouly <joey.gouly@arm.com>
| |