Messages in this thread Patch in this message | | | From | Ravi Gunasekaran <> | Subject | [PATCH v13 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe | Date | Thu, 9 Mar 2023 13:59:40 +0530 |
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From: Aswath Govindraju <a-govindraju@ti.com>
x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same.
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> --- Changes from v12: * No change
Changes from v11: * No change
Changes from v10: * Removed Link tag from commit message
Changes from v9: * No change
Changes from v8: * No change
Changes from v7: * No change
Changes from v6: * Removed pcie_ep node update
Changes from v5: * No change
Changes from v4: * No change
Changes from v3: * No change
Changes from v2: * Patch newly added to the series
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index ede8857db7c9..cd3013354493 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -375,6 +375,14 @@ }; }; +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- 2.17.1
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