Messages in this thread | | | Date | Wed, 8 Mar 2023 11:03:35 +0000 | From | Conor Dooley <> | Subject | Re: [PATCH] Revert "riscv: Set more data to cacheinfo" |
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On Wed, Mar 08, 2023 at 02:47:34PM +0800, Song Shuai wrote: > This reverts commit baf7cbd94b5688f167443a2cc3dcea3300132099. > > There are some duplicate cache attributes populations executed > in both ci_leaf_init() and later cache_setup_properties(). > > Revert the commit baf7cbd94b56 ("riscv: Set more data to cacheinfo") > to setup only the level and type attributes at this early place. >
I've attempted to do a little bit of history diving to figure out what commit to "blame" in a fixes tag for this. My initial thought was to blame 03f11f03dbfe ("RISC-V: Parse cpu topology during boot."), but baf7cbd94b56 ("riscv: Set more data to cacheinfo") looks like it came along some months later. I assume you double checked that the stuff in the aux vector is the same before/after this revert? Looking on lore, that seems to be why Zong did it this way in the first place: https://lore.kernel.org/linux-riscv/b6fed9b4c2a3eacb2a9c353c2570d9dc1d0c1c88.1598859038.git.zong.li@sifive.com/
Cheers, Conor.
> Signed-off-by: Song Shuai <suagrfillet@gmail.com> > --- > arch/riscv/kernel/cacheinfo.c | 66 ++++++++--------------------------- > 1 file changed, 15 insertions(+), 51 deletions(-) > > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c > index 3a13113f1b29..305ebbdc780d 100644 > --- a/arch/riscv/kernel/cacheinfo.c > +++ b/arch/riscv/kernel/cacheinfo.c > @@ -64,53 +64,12 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type) > 0; > } > > -static void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type, > - unsigned int level, unsigned int size, > - unsigned int sets, unsigned int line_size) > +static void ci_leaf_init(struct cacheinfo *this_leaf, > + struct device_node *node, > + enum cache_type type, unsigned int level) > { > this_leaf->level = level; > this_leaf->type = type; > - this_leaf->size = size; > - this_leaf->number_of_sets = sets; > - this_leaf->coherency_line_size = line_size; > - > - /* > - * If the cache is fully associative, there is no need to > - * check the other properties. > - */ > - if (sets == 1) > - return; > - > - /* > - * Set the ways number for n-ways associative, make sure > - * all properties are big than zero. > - */ > - if (sets > 0 && size > 0 && line_size > 0) > - this_leaf->ways_of_associativity = (size / sets) / line_size; > -} > - > -static void fill_cacheinfo(struct cacheinfo **this_leaf, > - struct device_node *node, unsigned int level) > -{ > - unsigned int size, sets, line_size; > - > - if (!of_property_read_u32(node, "cache-size", &size) && > - !of_property_read_u32(node, "cache-block-size", &line_size) && > - !of_property_read_u32(node, "cache-sets", &sets)) { > - ci_leaf_init((*this_leaf)++, CACHE_TYPE_UNIFIED, level, size, sets, line_size); > - } > - > - if (!of_property_read_u32(node, "i-cache-size", &size) && > - !of_property_read_u32(node, "i-cache-sets", &sets) && > - !of_property_read_u32(node, "i-cache-block-size", &line_size)) { > - ci_leaf_init((*this_leaf)++, CACHE_TYPE_INST, level, size, sets, line_size); > - } > - > - if (!of_property_read_u32(node, "d-cache-size", &size) && > - !of_property_read_u32(node, "d-cache-sets", &sets) && > - !of_property_read_u32(node, "d-cache-block-size", &line_size)) { > - ci_leaf_init((*this_leaf)++, CACHE_TYPE_DATA, level, size, sets, line_size); > - } > } > > int populate_cache_leaves(unsigned int cpu) > @@ -121,24 +80,29 @@ int populate_cache_leaves(unsigned int cpu) > struct device_node *prev = NULL; > int levels = 1, level = 1; > > - /* Level 1 caches in cpu node */ > - fill_cacheinfo(&this_leaf, np, level); > + if (of_property_read_bool(np, "cache-size")) > + ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); > + if (of_property_read_bool(np, "i-cache-size")) > + ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); > + if (of_property_read_bool(np, "d-cache-size")) > + ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); > > - /* Next level caches in cache nodes */ > prev = np; > while ((np = of_find_next_cache_node(np))) { > of_node_put(prev); > prev = np; > - > if (!of_device_is_compatible(np, "cache")) > break; > if (of_property_read_u32(np, "cache-level", &level)) > break; > if (level <= levels) > break; > - > - fill_cacheinfo(&this_leaf, np, level); > - > + if (of_property_read_bool(np, "cache-size")) > + ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); > + if (of_property_read_bool(np, "i-cache-size")) > + ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); > + if (of_property_read_bool(np, "d-cache-size")) > + ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); > levels = level; > } > of_node_put(np); > -- > 2.20.1 > [unhandled content-type:application/pgp-signature] | |