Messages in this thread | | | Date | Wed, 8 Mar 2023 11:22:27 +0530 | Subject | Re: [PATCH 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes | From | Varadarajan Narayanan <> |
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On 3/7/2023 5:19 PM, Dmitry Baryshkov wrote: > On 07/03/2023 08:36, Varadarajan Narayanan wrote: >> >> On 3/6/2023 5:21 PM, Dmitry Baryshkov wrote: >>> On 06/03/2023 13:26, Varadarajan Narayanan wrote: >>>> Dmitry, >>>> >>>> On 3/2/2023 9:52 PM, Dmitry Baryshkov wrote: >>>>> On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan >>>>> <quic_varada@quicinc.com> wrote: >>>>>> Add USB phy and controller related nodes >>>>>> >>>>>> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> >>>>>> --- >>>>>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92 >>>>>> +++++++++++++++++++++++++++++++++++ >>>>>> 1 file changed, 92 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >>>>>> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >>>>>> index 2bb4053..319b5bd 100644 >>>>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >>>>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >>> >>> [skipped] >>> >>> >>>>>> + usb3: usb3@8A00000 { >>>>> You know the drill. This node is in the wrong place. >>>>> >>>>>> + compatible = "qcom,dwc3"; >>>>>> + reg = <0x8AF8800 0x400>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <1>; >>>>>> + ranges; >>>>>> + >>>>>> + clocks = <&gcc GCC_SNOC_USB_CLK>, >>>>>> + <&gcc GCC_ANOC_USB_AXI_CLK>, >>>>>> + <&gcc GCC_USB0_MASTER_CLK>, >>>>>> + <&gcc GCC_USB0_SLEEP_CLK>, >>>>>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>; >>>>>> + >>>>>> + clock-names = "sys_noc_axi", >>>>>> + "anoc_axi", >>>>>> + "master", >>>>>> + "sleep", >>>>>> + "mock_utmi"; >>>>> Please fix the indentation of the lists. >>>>> >>>>>> + >>>>>> + assigned-clocks = <&gcc GCC_SNOC_USB_CLK>, >>>>>> + <&gcc >>>>>> GCC_ANOC_USB_AXI_CLK>, >>>>> Why do you assign clock rates to the NOC clocks? Should they be set >>>>> using the interconnect instead? >>>> >>>> The SNOC and ANOC run at a fixed speed of 350MHz and 342MHz >>>> respectively and are not scaled. These clocks are for the interface >>>> between the USB block and the SNOC/ANOC. Do we still need to use >>>> interconnect? >>> >>> Maybe I misunderstand something here. If the snoc and anoc speeds >>> are at 350 MHz and 342 MHz, why do you assign clock-rates of 200 MHz? >>> >>> Is it enough to call clk_prepare_enable() for these clocks or the >>> rate really needs to be set? >> >> The rate of 200MHz is not being set for the SNOC/ANOC. It is for the >> NIU that connects the USB and SNOC/ANOC. The reason for setting the >> rate to 200MHz is to configure the RCG parent for these interface >> clocks. That said can we configure this RCG standalone in the driver >> and enable these clocks? > > We discussed this separately with Georgi Djakov. Let me quote his IRC > message: "it sounds like this is for USB port that connects to the > NOC. if bandwidth scaling is not needed (or other interconnect > configuration), then maybe this can go without interconnect provider > driver." > > However as we discover more and more about this platform (e.g. PCIe > using the aggre_noc region to setup some magic registers, see [1]), > I'm more and more biased towards suggesting implementing the > interconnect driver to setup all these tiny little things. With the DT > tree being an ABI, it is much preferable to overestimate the needs > rather than underestimating them (and having to cope with the > backwards compatibility issues). > > Generally I think that PCIe/USB/whatever should not poke into NoC > registers or NoC/NIU clocks directly (because this is a very > platform-specific item). Rather than that it should tell the > icc/opp/whatever subsystem, "please configure the SoC for me to work". > > [1] > https://lore.kernel.org/linux-arm-msm/30cf9717-dcca-e984-c506-c71b7f8e32cd@quicinc.com/
Sure, will post a new revision that uses interconnect subsystem.
Thanks Varada
>>>>>> + <&gcc GCC_USB0_MASTER_CLK>, >>>>>> + <&gcc >>>>>> GCC_USB0_MOCK_UTMI_CLK>; >>>>>> + assigned-clock-rates = <200000000>, >>>>>> + <200000000>, >>>>>> + <200000000>, >>>>>> + <24000000>; >>>>>> + >>>>>> + resets = <&gcc GCC_USB_BCR>; >>>>>> + status = "disabled"; >>>>>> + >>>>>> + dwc_0: dwc3@8A00000 { >>>>>> + compatible = "snps,dwc3"; >>>>>> + reg = <0x8A00000 0xcd00>; >>>>>> + clock-names = "ref"; >>>>>> + clocks = <&gcc >>>>>> GCC_USB0_MOCK_UTMI_CLK>; >>>>> clocks before clock-names >>>>> >>>>>> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + phys = <&qusb_phy_0>, <&usb0_ssphy>; >>>>>> + phy-names = "usb2-phy", "usb3-phy"; >>>>>> + tx-fifo-resize; >>>>>> + snps,dis_ep_cache_eviction; >>>>>> + snps,is-utmi-l1-suspend; >>>>>> + snps,hird-threshold = /bits/ 8 >>>>>> <0x0>; >>>>>> + snps,dis_u2_susphy_quirk; >>>>>> + snps,dis_u3_susphy_quirk; >>>>>> + snps,quirk-frame-length-adjustment = <0x0A87F0A0>; >>>>>> + dr_mode = "host"; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> pcie0_phy: phy@84000 { >>>>>> compatible = >>>>>> "qcom,ipq9574-qmp-gen3x1-pcie-phy"; >>>>>> reg = <0x00084000 0x1bc>; /* Serdes PLL */ >>>>>> -- >>>>>> 2.7.4 >>>> >>>> Will address these and post a new revision. >>>> >>>> Thanks >>>> >>>> Varada >>>> >>> >
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