Messages in this thread | | | From | "Mahapatra, Amit Kumar" <> | Subject | RE: [PATCH V5 09/15] spi: Add stacked and parallel memories support in SPI core | Date | Tue, 7 Mar 2023 11:37:50 +0000 |
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> -----Original Message----- > From: Tudor Ambarus <tudor.ambarus@linaro.org> > Sent: Tuesday, March 7, 2023 9:51 AM > To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@amd.com>; > broonie@kernel.org; miquel.raynal@bootlin.com; richard@nod.at; > vigneshr@ti.com; jic23@kernel.org; pratyush@kernel.org > Cc: linux-spi@vger.kernel.org; linux-mtd@lists.infradead.org; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH V5 09/15] spi: Add stacked and parallel memories > support in SPI core > > There were too many recipients in To and Cc and I couldn't reply to the > email. I whipped off the Cc filed and most of the people from To and added > the lists in Cc. > > On 3/6/23 17:21, Amit Kumar Mahapatra wrote: > > Multi CS support using GPIO is not tested due to unavailability of > > necessary hardware setup. > > Please don't add code that is not used or tested.
During our discussion on the RFC, Mark had suggested to add multi-cs support via GPIO as well. We had agreed to add multi-cs support via GPIO, but had also mentioned that we don't have a hardware setup to test the CS GPIO use case. https://lore.kernel.org/linux-arm-kernel/BN7PR12MB2802E2A9079E505932832270DC979@BN7PR12MB2802.namprd12.prod.outlook.com/
Regards, Amit
> > Cheers, > ta
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