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Subject[PATCH v2 3/6] dt-bindings: clk: Add Hi3798MV100 CRG driver binding
Date
Add CRG driver for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module
generates clock and reset signals used by other module blocks on SoC.

Signed-off-by: David Yang <mmyangfl@gmail.com>
---
Documentation/devicetree/bindings/clock/hisi-crg.txt | 2 ++
include/dt-bindings/clock/histb-clock.h | 10 ++++++++++
2 files changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt
index cc60b3d42..972c038c8 100644
--- a/Documentation/devicetree/bindings/clock/hisi-crg.txt
+++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt
@@ -13,6 +13,8 @@ Required Properties:
- "hisilicon,hi3516cv300-crg"
- "hisilicon,hi3516cv300-sysctrl"
- "hisilicon,hi3519-crg"
+ - "hisilicon,hi3798mv100-crg"
+ - "hisilicon,hi3798mv100-sysctrl"
- "hisilicon,hi3798cv200-crg"
- "hisilicon,hi3798cv200-sysctrl"

diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
index e64e5770a..5042c2a7a 100644
--- a/include/dt-bindings/clock/histb-clock.h
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -58,6 +58,16 @@
#define HISTB_USB3_UTMI_CLK1 48
#define HISTB_USB3_PIPE_CLK1 49
#define HISTB_USB3_SUSPEND_CLK1 50
+#define HISTB_USB2_UTMI_CLK1 51
+#define HISTB_USB2_2_BUS_CLK 52
+#define HISTB_USB2_2_PHY_CLK 53
+#define HISTB_USB2_2_UTMI_CLK 54
+#define HISTB_USB2_2_UTMI_CLK1 55
+#define HISTB_USB2_2_12M_CLK 56
+#define HISTB_USB2_2_48M_CLK 57
+#define HISTB_USB2_2_OTG_UTMI_CLK 58
+#define HISTB_USB2_2_PHY1_REF_CLK 59
+#define HISTB_USB2_2_PHY2_REF_CLK 60

/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1
--
2.39.2
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