Messages in this thread | | | Date | Fri, 31 Mar 2023 12:59:57 +0200 | Subject | Re: [PATCH v9 11/11] arm64: dts: mediatek: mt8195: Add SCP 2nd core | From | Matthias Brugger <> |
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On 28/03/2023 04:27, Tinghan Shen wrote: > Rewrite the MT8195 SCP device node as a cluster and > add the SCP 2nd core in it. > > Since the SCP device node is changed to multi-core structure, > enable SCP cluster to enable probing SCP core 0. > > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
As this is a bigger change I'd prefer to take it through my tree once the driver and dt-bindings changes are merged. Given the fact, maybe it would make sense to take 2/11 through my tree as well.
Regards, Matthias
> --- > .../boot/dts/mediatek/mt8195-cherry.dtsi | 6 +++- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 32 ++++++++++++++----- > 2 files changed, 29 insertions(+), 9 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi > index 56749cfe7c33..31415d71b6a4 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi > @@ -933,7 +933,11 @@ > interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; > }; > > -&scp { > +&scp_cluster { > + status = "okay"; > +}; > + > +&scp_c0 { > status = "okay"; > > firmware-name = "mediatek/mt8195/scp.img"; > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 8fc527570791..5fe5fb32261e 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -826,14 +826,30 @@ > clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; > }; > > - scp: scp@10500000 { > - compatible = "mediatek,mt8195-scp"; > - reg = <0 0x10500000 0 0x100000>, > - <0 0x10720000 0 0xe0000>, > - <0 0x10700000 0 0x8000>; > - reg-names = "sram", "cfg", "l1tcm"; > - interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; > + scp_cluster: scp@10500000 { > + compatible = "mediatek,mt8195-scp-dual"; > + reg = <0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>; > + reg-names = "cfg", "l1tcm"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0x10500000 0x100000>; > status = "disabled"; > + > + scp_c0: scp@0 { > + compatible = "mediatek,scp-core"; > + reg = <0x0 0xa0000>; > + reg-names = "sram"; > + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; > + status = "disabled"; > + }; > + > + scp_c1: scp@a0000 { > + compatible = "mediatek,scp-core"; > + reg = <0xa0000 0x20000>; > + reg-names = "sram"; > + interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; > + status = "disabled"; > + }; > }; > > scp_adsp: clock-controller@10720000 { > @@ -2309,7 +2325,7 @@ > <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, > <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; > interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; > - mediatek,scp = <&scp>; > + mediatek,scp = <&scp_c0>; > clocks = <&vencsys CLK_VENC_VENC>; > clock-names = "venc_sel"; > assigned-clocks = <&topckgen CLK_TOP_VENC>;
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