Messages in this thread | | | Date | Fri, 31 Mar 2023 09:24:29 +0100 | From | "Russell King (Oracle)" <> | Subject | Re: [PATCH net-next 2/2] net: ethernet: ti: am65-cpsw: Enable USXGMII mode for J784S4 CPSW9G |
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On Fri, Mar 31, 2023 at 01:35:10PM +0530, Siddharth Vadapalli wrote: > Hello Russell, > > Thank you for reviewing the patch. > > On 31/03/23 13:27, Russell King (Oracle) wrote: > > On Fri, Mar 31, 2023 at 12:21:10PM +0530, Siddharth Vadapalli wrote: > >> TI's J784S4 SoC supports USXGMII mode. Add USXGMII mode to the > >> extra_modes member of the J784S4 SoC data. Additionally, configure the > >> MAC Control register for supporting USXGMII mode. Also, for USXGMII > >> mode, include MAC_5000FD in the "mac_capabilities" member of struct > >> "phylink_config". > > > > I don't think TI "get" phylink at all... > > > >> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c > >> index 4b4d06199b45..ab33e6fe5b1a 100644 > >> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c > >> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c > >> @@ -1555,6 +1555,8 @@ static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy > >> mac_control |= CPSW_SL_CTL_GIG; > >> if (interface == PHY_INTERFACE_MODE_SGMII) > >> mac_control |= CPSW_SL_CTL_EXT_EN; > >> + if (interface == PHY_INTERFACE_MODE_USXGMII) > >> + mac_control |= CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN; > > > > The configuration of the interface mode should *not* happen in > > mac_link_up(), but should happen in e.g. mac_config(). > > I will move all the interface mode associated configurations to mac_config() in > the v2 series.
Looking at the whole of mac_link_up(), could you please describe what effect these bits are having:
CPSW_SL_CTL_GIG CPSW_SL_CTL_EXT_EN CPSW_SL_CTL_IFCTL_A
Thanks.
-- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
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