Messages in this thread | | | Date | Fri, 31 Mar 2023 10:53:19 +0300 | Subject | Re: [PATCH 1/2] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4 | From | Roger Quadros <> |
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On 31/03/2023 10:49, Siddharth Vadapalli wrote: > Hello Roger, > > On 31/03/23 13:15, Roger Quadros wrote: >> >> >> On 31/03/2023 09:25, Siddharth Vadapalli wrote: >>> Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII. >>> >>> Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports" >>> property for J784S4. >>> >>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >>> --- >>> drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++ >>> 1 file changed, 13 insertions(+) >>> >>> diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c >>> index c87118cb2af9..fba5c0c0771c 100644 >>> --- a/drivers/phy/ti/phy-gmii-sel.c >>> +++ b/drivers/phy/ti/phy-gmii-sel.c >>> @@ -235,6 +235,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { >>> .num_qsgmii_main_ports = 2, >>> }; >>> >>> +static const >>> +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { >> >> Please make it into one line > > I was simply following the convention used for other SoC data structs in the > same file. Please let me know why this has to be an exception and I will post > the v2 series with the change accordingly.
Not that much of a deal. ;)
Reviewed-by: Roger Quadros <rogerq@kernel.org>
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